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71256SA15PZG

P1-P3P4-P6P7-P8
4
IDT71256SA
CMOS Static RAM 256K (32K x 8-Bit) Commercial and Industrial Temperature Ranges
AC Electrical Characteristics (VCC = 5.0V ± 10%)
NOTE:
1. This parameter is guaranteed with the AC Load (Figure 2) by device characterization, but is not production tested.
Symbol Parameter
71256SA12 71256SA15 71256SA20 71256SA25
Unit
Min. Max. Min. Max. Min. Max. Min. Max.
Read Cycle
t
RC
Read Cycle Time 12
____
15
____
20
____
25
____
ns
t
AA
Address Access Time
____
12
____
15
____
20
____
25 ns
t
ACS
Chip Select Access Time
____
12
____
15
____
20
____
25 ns
t
CL Z
(1 )
Chip Select to Output in Low-Z 4
____
4
____
4
____
4
____
ns
t
CHZ
(1 )
Chip Select to Output in High-Z 0 6 0 7 0 10 0 11 ns
t
OE
Output Enable to Output Valid
____
6
____
7
____
10
____
11 ns
t
OLZ
(1)
Output Enable to Output in Low-Z 0
____
0
____
0
____
0
____
ns
t
OHZ
(1 )
Output Disable to Output in High-Z 060608010ns
t
OH
Output Hold from Address Change 3
____
3
____
3
____
3
____
ns
t
PU
(1)
Chip Select to Power Up Time 0
____
0
____
0
____
0
____
ns
t
PD
(1)
Chip Deselect to Power Down Time
____
12
____
15
____
20
____
25 ns
Write Cycle
t
WC
Write Cycle Time 12
____
15
____
20
____
25
____
ns
t
AW
Address Valid to End-of-Write 9
____
10
____
15
____
20
____
ns
t
CW
Chip Select to End-of-Write 9
____
10
____
15
____
20
____
ns
t
AS
Address Set-up Time 0
____
0
____
0
____
0
____
ns
t
WP
Write Pulse Width 8
____
10
____
15
____
20
____
ns
t
WR
Write Recovery Time 0
____
0
____
0
____
0
____
ns
t
DW
Data Valid to End-of-Write 6
____
7
____
11
____
13
____
ns
t
DH
Data Hold Time 0
____
0
____
0
____
0
____
ns
t
OW
(1)
Output Active from End-of-Write 4
____
4
____
4
____
4
____
ns
t
WHZ
(1)
Write Enable to Output in High-Z 0 6 0 6 0 10 0 11 ns
2948 tbl 09
6.42
IDT71256SA
CMOS Static RAM 256K (32K x 8-Bit) Commercial and Industrial Temperature Ranges
5
Timing Waveform of Read Cycle No. 1
(1)
ADDRESS
OE
CS
DATA
OUT
V
CC
SUPPLY
CURRENT
2948 drw 05
(5)
(5)
(5)
(5)
DATA VALID
HIGH IMPEDANCE
t
AA
t
RC
t
OE
t
ACS
t
OLZ
t
CHZ
t
CLZ
(3)
t
OHZ
OUT
t
PU
t
PD
I
CC
I
SB
,
Timing Waveform of Read Cycle No. 2
(1,2,4)
NOTES:
1. WE is HIGH for Read Cycle.
2. Device is continuously selected, CS is LOW.
3. Address must be valid prior to or coincident with the later of CS transition LOW; otherwise tAA is the limiting parameter.
4. OE is LOW.
5. Transition is measured ±200mV from steady state.
DATA
OUT
ADDRESS
2948 drw 06
t
RC
t
AA
t
OH
t
OH
DATA
OUT
VALID
PREVIOUS DATA
OUT
VALID
,
6
IDT71256SA
CMOS Static RAM 256K (32K x 8-Bit) Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)
(1,2,4)
NOTES:
1. A write occurs during the overlap of a LOW CS and a LOW WE.
2. OE is continuously HIGH. If during a WE controlled write cycle OE is LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and data
to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is as
short as the specified tWP.
3. During this period, I/O pins are in the output state, and input signals must not be applied.
4. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.
5. Transition is measured ±200mV from steady state.
Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)
(1,4)
ADDRESS
CS
WE
DATA
OUT
DATA
IN
2948 drw 07
(5)
(3)
(3)
(2)
(5)
(5)
DATA
IN
VALID
HIGH IMPEDANCE
t
WC
t
AS
t
WHZ
t
WP
t
CHZ
t
OW
t
DW
t
WR
t
AW
t
DH
,
CS
ADDRESS
WE
2948 drw 08
DATA
IN
VALID
t
AW
t
WC
t
CW
t
AS
t
WR
t
DW
t
DH
DATA
IN
,
P1-P3P4-P6P7-P8

71256SA15PZG

Mfr. #:
Buy 71256SA15PZG
Manufacturer:
IDT
Description:
SRAM 32Kx8 ASYNCHRONOUS 5.0V STATIC RAM
Lifecycle:
New from this manufacturer.
Delivery:
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