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MC100H640FNR2G

P1-P3P4-P6P7-P8
MC10H640
www.onsemi.com
4
Table 5. AC CHARACTERISTICS (V
T
= V
E
= 5.0 V ±5%)
Symbol
Characteristic Condition
0°C 25°C 85°C
Unit
Min Max Min Max Min Max
t
PLH
Propagation Delay ECL
D to Output
Q0 − Q3 CL = 25 pF 4.0 6.0 4.0 6.0 4.2 6.2 ns
t
PLH
Propagation Delay TTL
D to Output
CL = 25 pF 4.0 6.0 4.0 6.0 4.3 6.3 ns
tskwd* Within-Device Skew CL = 25 pF 0.5 0.5 0.5 ns
t
PLH
Propagation Delay ECL
D to Output
Q0, Q1 CL = 25 pF 4.0 6.0 4.0 6.0 4.2 6.2 ns
t
PLH
Propagation Delay TTL
D to Output
CL = 25 pF 4.0 6.0 4.0 6.0 4.3 6.3 ns
t
PLH
Propagation Delay ECL
D to Output
Q4, Q5 CL = 25 pF 4.0 6.0 4.0 6.0 4.2 6.2 ns
t
PLH
Propagation Delay TTL
D to Output
CL = 25 pF 4.0 6.0 4.0 6.0 4.3 6.3 ns
t
PD
Propagation Delay
R to Output
All Outputs CL = 25 pF 4.3 6.3 4.3 6.3 5.0 7.0 ns
t
R
t
F
Output Rise/Fall Time
0.8 V to 2.0 V
All Outputs CL = 25 pF 2.5
2.5
2.5
2.5
2.5
2.5
ns
f
max
Maximum Input Frequency CL = 25 pF 135 135 135 MHz
t
pw
Minimum Pulse Width 1.50 1.50 1.50 ns
t
rr
Reset Recovery Time 1.25 1.25 1.25 ns
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. Within-Device Skew defined as identical transitions on similar paths through a device.
Table 6. V
CC
and C
L
RANGES TO MEET DUTY CYCLE REQUIREMENTS
(0°C ≤ T
A
≤ 85°C Output Duty Cycle Measured Relative to 1.5 V)
Symbol
Characteristic Condition Min Nom Max Unit
Range of V
CC
and CL to meet mini-
mum pulse width
(HIGH or LOW)
= 11.5 ns at f
out
≤ 40 MHz
V
CC
CL
Q0 − Q3
Q0 − Q1
4.75
10
5.0 5.25
50
V
pF
Range of V
CC
and CL to meet mini-
mum pulse width
(HIGH or LOW)
= 9.5 ns at 40 < f
out
≤ 50 MHz
V
CC
CL
Q0 − Q3 4.875
15
5.0 5.125
27
V
pF
MC10H640
www.onsemi.com
5
10
11
9
0 25507585
5.25 V
CC
5 V
CC
4.75 V
CC
PW (ns)
Figure 3. Positive Pulse Width at
25°C Ambient and 50 MHz Out
LOAD
(pF)
10
11
9
025507585
Figure 4. Negative Pulse Width at
25°C Ambient and 50 MHz Out
LOAD (pF)
NEGATIVE PULSE WIDTH (ns)
4.75 V
CC
5 V
CC
5.25 V
CC
10H640
DUTY CYCLE CONTROL
To maintain a duty cycle of ±5% at 50MHz, limit the load capacitance and/or power supply variation as shown in Figures 3
and 4. Figure 5 shows typical TPD versus load. Figure 6 shows reset recovery time. Figure 7 shows output states after power
up. Best duty cycle control is obtained with a single mP load and minimum line length.
Resource Reference of Application Notes
AN1405/D − ECL Clock Distribution Techniques
AN1406/D − Designing with PECL (ECL at +5.0 V)
AN1503/D −
ECLinPSt I/O SPiCE Modeling Kit
AN1504/D − Metastability and the ECLinPS Family
AN1568/D − Interfacing Between LVDS and ECL
AN1672/D − The ECL Translator Guide
AND8001/D − Odd Number Counters Design
AND8002/D − Marking and Date Codes
AND8020/D − Termination of ECL Logic Devices
AND8066/D − Interfacing with ECLinPS
AND8090/D − AC Characteristics of ECL Devices
MC10H640
www.onsemi.com
6
5.8
6.2
5.4
0
25
50 75 85
Figure 5. t
PD
versus Load Typical at T
A
= 25°C
t
PD
C
LOAD
(pF)
4.75
V
5
V
5.25
V
Figure 6. MC10H640 Clock Phase and
Reset Recovery Time After Reset Pulse
DT
RESET, R
Q0, Q1, Q2, Q3
Q0
, Q1
Q4, Q5
R
trec
R
tpw
Figure 7. Output Timing Diagram
AFTER POWER UP
OUTPUTS Q
4
& Q
5
WILL SYNC WITH POSITIVE EDGES OF D
in
& Q
0
→ Q
3
& NEGATIVE EDGES OF Q
0
& Q
1
D
in
Q
0
→ Q
3
Q
1
→ Q
2
Q
4
& Q
5
5.2
5.6
6.0
(ns)
P1-P3P4-P6P7-P8

MC100H640FNR2G

Mfr. #:
Buy MC100H640FNR2G
Manufacturer:
ON Semiconductor
Description:
Clock Drivers & Distribution BBG ECLClock Driver
Lifecycle:
New from this manufacturer.
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