4
IX4R11
Figure 3. INPUT/OUPUT Timing Diagram
Symbol Definition Test Conditions Min Typ Max Units
V
INH
Logic “1” input voltage V
DD
= V
CL
= 15V 7.0 V
V
INL
Logic “0” input voltage V
DD
= V
CC
= 15V 6 V
V
HLGO /
/ V
HHGO
High level output voltage, I
O
= 0A 0.28 V
V
CH
-V
HGO
or V
CL
-V
LGO
V
LLGO /
/ V
LHGO
High level output voltage, I
O
= 0A .23 V
V
HGO
or V
LGO
I
HL
HS to LS bias current. V
HS
= V
CH
= 600V .17 mA
I
QHS
Quiescent V
CH
supply current V
IN
= 0V or V
DD
.77 mA
I
QLS
Quiescent V
CL
supply current V
IN
= 0V or V
DD
.79 mA
I
QDD
Quiescent V
DD
supply current V
IN
= 0V or V
DD
36 uA
I
IN
+ Logic “1” input bias current V
IN
= V
DD
2uA
I
IN
- Logic “0” input voltage V
IN
= 0V 1 uA
V
CHUV
+V
CH
supply undervoltage positive going threshold. 8.3 V
V
CHUV
-V
CH
supply undervoltage negative going threshold. 8.2 V
V
CLUV
+V
CL
supply undervoltage positive going threshold 8.1 V
V
CLUV
-V
CL
supply undervoltage negative going threshold. 8.0 V
I
GO
+ HS or LS Output low short circuit current; V
GO
= 15V, V
IN
= 0V, PW<10us +4 A
I
GO
- HS or LS Output low short circuit current; V
GO
= 15V, V
IN
=0V, PW<10us -4 A
Dynamic Electrical Characteristics
Symbol Definition Test Conditions Min Typ Max Units
t
on
Turn-on propagation delay V
HS
= 0V, C
load
= 2nF 120 ns
t
off
Turn-off propagation delay V
HS
= 600V, C
load
= 2nF 87 ns
t
en
Device enable delay 202 ns
t
r
Turn-on rise time C
load
= 2nF 23 ns
t
f
Turn-off fall time C
load
= 2nF 22 ns
t
dm
Delay matching, HS & LS turn-on/off C
load
= 2nF 10 20 ns
Static Electrical Characteristics
Figure 4. ENABLE Waveform Definitions
Timing Waveform Definitions
HIN/LIN
ENB
LGO/HGO
ENB
LGO/HGO
10%
50%
tenb
