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74ACT899QC

P1-P3P4-P6P7-P9
7 www.fairchildsemi.com
74ACT899
Absolute Maximum Ratings(Note 2)
Recommended Operating
Conditions
Note 2: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT circuits outside databook specifications.
DC Electrical Characteristics
Note 3: Maximum of 9 outputs loaded; thresholds on input associated with output under test.
Note 4: Maximum test duration 2.0 ms, one output loaded at a time.
Supply Voltage (V
CC
) −0.5V to +7.0V
DC Input Diode Current (I
IK
)
V
I
= −0.5V −20 mA
V
I
= V
CC
+ 0.5V +20 mA
DC Input Voltage (V
I
) −0.5V to V
CC
+ 0.5V
DC Output Diode Current (I
OK
)
V
O
= −0.5V −20 mA
V
O
= V
CC
+ 0.5V +20 mA
DC Output Voltage (V
O
) −0.5V to V
CC
+ 0.5V
DC Output Source
or Sink Current (I
O
) ±50 mA
DC V
CC
or Ground Current
per Output Pin (I
CC
or I
GND
) ±50 mA
Storage Temperature (T
STG
) −65°C to +150°C
DC Latch-Up Source or
Sink Current ±300 mA
Junction Temperature (T
J
)140°C
Supply Voltage (V
CC
) 4.5V to 5.5V
Input Voltage (V
I
) 0V to V
CC
Output Voltage (V
O
) 0V to V
CC
Operating Temperature (T
A
) −40°C to +85°C
Minimum Input Edge Rate ∆V/∆t 125 mV/ns
V
IN
from 0.8V to 2.0V
V
CC
@ 4.5V, 5.5V
Symbol Parameter
V
CC
T
A
= +25°CT
A
= −40°C to +85°C
Units Conditions
(V) Typ Guaranteed Limits
V
IH
Minimum HIGH Level 4.5 1.5 2.0 2.0 V V
OUT
= 0.1V
Input Voltage 5.5 1.5 2.0 2.0 or V
CC
− 0.1V
V
IL
Maximum LOW Level 4.5 1.5 0.8 0.8 V V
OUT
= 0.1V
Input Voltage 5.5 1.5 0.8 0.8 or V
CC
− 0.1V
V
OH
Minimum HIGH Level 4.5 4.49 4.4 4.4 V I
OUT
= −50 µA
Output Voltage 5.5 5.49 5.4 5.4
V
IN
= V
IL
or V
IH
4.5 3.86 3.76 V I
OH
= −24 mA
5.5 4.86 4.76 I
OH
= −24 mA (Note 3)
V
OL
Maximum LOW Level 4.5 0.001 0.1 0.1 V I
OUT
= 50 µA
Output Voltage 5.5 0.001 0.1 0.1
V
IN
= V
IL
or V
IH
4.5 0.36 0.44 V I
OL
= 24 mA
5.5 0.36 0.44 I
OL
= 24 mA (Note 3)
I
IN
Maximum Input 5.5 ±0.1 ±1.0 µAV
I
= V
CC
, GND
Leakage Current
I
OZ
Maximum 3-STATE 5.5 ±0.5 ±5.0 µAV
I
= V
IL
, V
IH
Leakage Current V
O
= V
CC
, GND
I
CCT
Maximum I
CC
/Input 5.5 0.6 1.5 mA V
I
= V
CC
− 2.1V
I
OLD
Minimum Dynamic 5.5 75 mA V
OLD
= 1.65V Max
I
OHD
Output Current (Note 4) 5.5 −75 mA V
OHD
= 3.85V Min
I
CC
Maximum Quiescent 5.5 8.0 80.0 µAV
IN
= V
CC
Supply Current or GND
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74ACT899
AC Electrical Characteristics
Note 5: Voltage Range 5.0 is 5.0V ± 0.5V.
AC Operating Requirements
Note 6: Voltage Range 5.0 = 5.0V ± 0.5V.
Capacitance
V
CC
T
A
= +25°CT
A
= −40°C to +85°C
Symbol Parameter (V)
C
L
= 50 pF C
L
= 50 pF
Units Fig. No.
(Note 5) Min Typ Max Min Max
t
PLH
Propagation Delay 5.0 2.5 7.5 11.5 2.5 12.0 ns Figure 1
t
PHL
A
n
, B
n
to B
n
, A
n
t
PLH
Propagation Delay 5.0 1.5 6.0 8.5 1.5 9.0 ns Figure 1
t
PHL
APAR, BPAR to BPAR, APAR
t
PLH
Propagation Delay 5.0 2.5 8.5 12.0 2.5 12.5 ns Figure 2
t
PHL
A
n
, B
n
to BPAR, APAR
t
PLH
Propagation Delay 5.0 2.0 8.0 11.5 2.0 12.0 ns Figure 3
t
PHL
A
n
, B
n
to ERRA, ERRB
t
PLH
Propagation Delay 5.0 2.0 8.0 11.5 2.0 12.0 ns Figure 4
t
PHL
ODD/EVEN to ERRA, ERRB
t
PLH
Propagation Delay 5.0 2.5 8.0 11.5 2.5 12.0 ns Figure 5
t
PHL
ODD/EVEN to APAR, BPAR
t
PLH
Propagation Delay 5.0 1.5 7.5 10.5 1.5 11.5 ns Figure 6
t
PHL
APAR, BPAR to ERRA, ERRB
t
PLH
Propagation Delay 5.0 1.5 6.5 9.0 1.5 9.5 ns Figure 9
t
PHL
SEL to APAR, BPAR
t
PLH
Propagation Delay 5.0 2.5 7.0 10.5 2.5 11.0 ns Figure 10
t
PHL
LEB to A
n
, B
n
Figure 11
t
PLH
Propagation Delay 5.0 2.0 8.0 11.5 2.0 12.0 ns Figure 10
t
PHL
LEA to APAR, BPAR Figure 11
t
PLH
Propagation Delay 5.0 2.5 8.0 11.5 2.5 12.0 ns Figure 12
t
PHL
LEA, LEB to ERRA, ERRB
t
PZH
Output Enable Time 5.0 2.5 7.0 10.5 2.5 11.0 ns Figure 7
t
PZL
GBA or GAB to A
n
, B
n
Figure 8
t
PZH
Output Enable Time 5.0 1.5 6.0 9.0 1.5 9.5 ns Figure 7
t
PZL
GBA or GAB to BPAR or APAR
Figure 8
t
PHZ
Output Disable Time 5.0 1.5 6.5 9.5 1.5 9.5 ns Figure 7
t
PHL
GBA or GAB to A
n
, B
n
Figure 8
t
PHZ
Output Disable Time 5.0 1.5 6.5 9.5 1.5 9.5 ns Figure 7
t
PLZ
GBA or GAB to BPAR, APAR
Figure 8
V
CC
T
A
= +25°C T
A
= −40°C to +85°C
Symbol Parameter (V)
C
L
= 50 pF C
L
= 50 pF
Units Fig. No.
(Note 6) Guaranteed Minimum
t
S
Setup Time, HIGH or LOW 5.0 3.0 3.0 ns Figure 11
A
n
, B
n
, PAR to LEA, LEB Figure 12
t
H
Hold Time, HIGH or LOW 5.0 1.5 1.5 ns Figure 11
A
n
, B
n
, PAR to LEA, LEB Figure 12
t
W
Pulse Width for LEB, LEA 5.0 4.0 4.0 ns Figure 13
Symbol Parameter Typ Units Conditions
C
IN
Input Capacitance 4.5 pF V
CC
= 5.0V
C
PD
Power Dissipation Capacitance 210 pF V
CC
= 5.0V
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
74ACT899 9-Bit Latchable Transceiver with Parity Generator/Checker
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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Physical Dimensions inches (millimeters) unless otherwise noted
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450” Square
Package Number V28A
P1-P3P4-P6P7-P9

74ACT899QC

Mfr. #:
Buy 74ACT899QC
Manufacturer:
ON Semiconductor / Fairchild
Description:
Bus Transceivers 9-Bit Latch Trans
Lifecycle:
New from this manufacturer.
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