7
FN3676.5
September 30, 2015
HIP4082
Pin Descriptions
PIN
NUMBER SYMBOL DESCRIPTION
1 BHB B High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of bootstrap
diode and positive side of bootstrap capacitor to this pin.
2 BHI B High-side Input. Logic level input that controls BHO driver (Pin 16). BLI (Pin 3) high level input overrides BHI high
level input to prevent half-bridge shoot-through, see Truth Table. DIS (Pin 8) high level input overrides BHI high level
input. The pin can be driven by signal levels of 0V to 15V (no greater than V
DD
).
3 BLI B Low-side Input. Logic level input that controls BLO driver (Pin 14). If BHI (Pin 2) is driven high or not connected
externally then BLI controls both BLO and BHO drivers, with dead time set by delay currents at DEL (Pin 5). DIS (Pin
8) high level input overrides BLI high level input. The pin can be driven by signal levels of 0V to 15V (no greater than
V
DD
).
4 ALI A Low-side Input. Logic level input that controls ALO driver (Pin 13). If AHI (Pin 7) is driven high or not connected
externally then ALI controls both ALO and AHO drivers, with dead time set by delay currents at DEL (Pin 5). DIS (Pin
8) high level input overrides ALI high level input. The pin can be driven by signal levels of 0V to 15V (no greater than
V
DD
).
5 DEL Turn-on DELay. Connect resistor from this pin to V
SS
to set timing current that defines the dead time between drivers.
All drivers turn-off with no adjustable delay, so the DEL resistor guarantees no shoot-through by delaying the turn-on
of all drivers. The voltage across the DEL resistor is approximately Vdd -2V.
6V
SS
Chip negative supply, generally will be ground.
7 AHI A High-side Input. Logic level input that controls AHO driver (Pin 10). ALI (Pin 4) high level input overrides AHI high
level input to prevent half-bridge shoot-through, see Truth Table. DIS (Pin 8) high level input overrides AHI high level
input. The pin can be driven by signal levels of 0V to 15V (no greater than V
DD
).
8 DIS DISable input. Logic level input that when taken high sets all four outputs low. DIS high overrides all other inputs. When
DIS is taken low the outputs are controlled by the other inputs. The pin can be driven by signal levels of 0V to 15V (no
greater than V
DD
).
9 AHB A High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of bootstrap
diode and positive side of bootstrap capacitor to this pin.
10 AHO A High-side Output. Connect to gate of A High-side power MOSFET.
11 AHS A High-side Source connection. Connect to source of A High-side power MOSFET. Connect negative side of bootstrap
capacitor to this pin.
12 V
DD
Positive supply to control logic and lower gate drivers. De-couple this pin to V
SS
(Pin 6).
13 ALO A Low-side Output. Connect to gate of A Low-side power MOSFET.
14 BLO B Low-side Output. Connect to gate of B Low-side power MOSFET.
15 BHS B High-side Source connection. Connect to source of B High-side power MOSFET. Connect negative side of bootstrap
capacitor to this pin.
16 BHO B High-side Output. Connect to gate of B High-side power MOSFET.
HIP4082
8
FN3676.5
September 30, 2015
HIP4082
Timing Diagrams
FIGURE 1. INDEPENDENT MODE
FIGURE 2. BISTATE MODE
FIGURE 3. DISABLE FUNCTION
DIS=0
XLI
XHI
XLO
XHO
T
LPHL
T
HPHL
T
HPLH
T
LPLH
T
R
(10% - 90%)
T
F
(10% - 90%)
X = A OR B, A AND B HALVES OF BRIDGE CONTROLLER ARE INDEPENDENT
and UV
DIS=0
XLI
XHI = HI OR NOT CONNECTED
XLO
XHO
and UV
DIS or UV
XLI
XHI
XLO
XHO
T
DLPLH
T
DIS
T
DHPLH
T
REF-PW
HIP4082
9
FN3676.5
September 30, 2015
HIP4082
Performance Curves
FIGURE 4. I
DD
SUPPLY CURRENT vs TEMPERATURE AND
V
DD
SUPPLY VOLTAGE
FIGURE 5. V
DD
SUPPLY CURRENT vs TEMPERATURE AND
SWITCHING FREQUENCY (1000pF LOAD)
FIGURE 6. FLOATING (IXHB) BIAS CURRENT vs
FREQUENCY AND LOAD
FIGURE 7. GATE SOURCE/SINK PEAK CURRENT vs BIAS
SUPPLY VOLTAGE AT 25°C
FIGURE 8. GATE CURRENT vs TEMPERATURE,
NORMALIZED TO 25°C
FIGURE 9. V
DD
-V
OH
vs BIAS VOLTAGE TEMPERATURE
-60 -40 -20 0 20 40 60 80 100 120 140
1.5
1.75
2
2.25
2.5
2.75
3
3.25
3.5
JUNCTION TEMPERATURE (°C)
I
DD
SUPPLY CURRENT (mA)
V
DD
= 16V
V
DD
= 15V
V
DD
= 12V
V
DD
= 10V
V
DD
= 8V
-60 -40 -20 0 20 40 60 80 100 120 140
4
5
6
7
8
9
10
11
12
13
14
15
16
JUNCTION TEMPERATURE (°C)
I
DD
SUPPLY CURRENT (mA)
200kHz
100kHz
50kHz
10kHz
0 50 100 150 200
0
1
2
3
4
5
6
7
8
FREQUENCY (kHz)
LOADED, NL BIAS CURRENTS (mA)
1000pF LOAD
NO LOAD
8 9 10 11 12 13 14 15
0.5
0.75
1
1.25
1.5
1.75
BIAS SUPPLY VOLTAGE (V) AT 25°C
PEAK GATE CURRENT (A)
1.925
0.815
I
SRC
(BIAS
)
I
SNK
(BIAS)
BIAS
2
8
15
SOURCE
SINK
-75 -50 -25 0 25 50 75 100 125 150
0.8
0.9
1
1.1
1.2
JUNCTION TEMPERATURE (°C)
NORMALIZED GATE
SINK/SOURCE CURRENT (A)
8 9 10 11 12 13 14 15
0.6
1
1.4
V
DD
SUPPLY VOLTAGE (V)
V
DD
-V
OH
(V)
1.2
0.8
-55°C
-40°C
0°C
25°C
125°C
150°C

HIP4082IBT

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Gate Drivers TAPE & VER OF STDARD HIP4082IB
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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