MP28115DQ-LF-Z

MP28115 – 4A, 1.5MHz SYNCHRONOUS STEP-DOWN CONVERTER
MP28115 Rev. 0.92 www.MonolithicPower.com 7
1/6/2016 MPS Proprietary Information. Patent Protected.
Unauthorized Photocopy and Duplication Prohibited.
© 2016 MPS. All Rights Reserved.
FUNCTIONAL DESCRIPTION
PWM Control
The MP28115 is a constant frequency peak-
current-mode control PWM switching regulator.
Refer to the functional block diagram, The high
side N-Channel DMOS power switch is turns on
at the beginning of each clock cycle. The current
in the inductor increases until the PWM current
comparator trips to turn off the high side DMOS
switch. The peak inductor current at which the
current comparator shuts off the high side power
switch is controlled by the COMP voltage at the
output of feedback error amplifier. The
transconductance from the COMP voltage to the
output current is set at 11.25A/V.
This current-mode control greatly simplifies the
feedback compensation design by approximating
the switching converter as a single-pole system.
Only Type II compensation network is needed,
which is integrated into the MP28115. The loop
bandwidth is adjusted by changing the upper
resistor value of the resistor divider at the FB pin.
The internal compensation in the MP28115
simplifies the compensation design, minimizes
external component counts, and keeps the
flexibility of external compensation for optimal
stability and transient response.
Enable and Frequency Synchronization
(EN/SYNC PIN)
This is a dual function input pin. Forcing this pin
below 0.4V for longer than 4μs shuts down the
part; forcing this pin above 1.6V for longer than
4µs turns on the part. Applying a 1MHz to 2MHz
clock signal to this pin also synchronizes the
internal oscillator frequency to the external clock.
When the external clock is used, the part turns
on after detecting the first few clocks regardless
of duty cycles. If any ON or OFF period of the
clock is longer than 4µs, the signal will be
intercepted as an enable input and disables the
synchronization.
Soft-Start and Output Pre-Bias Startup
When the soft-start period starts, an internal
current source begins charging an internal soft-
start capacitor. During soft-start the voltage on
the soft-start capacitor is connected to the non-
inverting input of the error amplifier. The soft-start
period lasts until the voltage on the soft-start
capacitor exceeds the reference voltage of 0.8V.
At this point the reference voltage takes over at
the non-inverting error amplifier input. The soft-
start time is internally set at 120µs. If the output
of the MP28115 is pre-biased to a certain voltage
during startup, the IC will disable the switching of
both high-side and low-side switches until the
voltage on the internal soft-start capacitor
exceeds the sensed output voltage at the FB pin.
Over current Protection
The MP28115 offers cycle-to-cycle current
limiting for both high-side and low-side switches.
The high-side current limit is relatively constant
regardless of duty cycles. When the output is
shorted to ground, causing the output voltage to
drop below 70% of its nominal output, the IC is
shut down momentarily and begins discharging
the soft start capacitor. It will restart with a full
soft-start when the soft- start capacitor is fully
discharged. This hiccup process is repeated until
the fault is removed.
Power Good Output (POK PIN)
The MP28115 includes an open-drain Power
Good output that indicates whether the regulator
output is within ±10% of its nominal output. When
the output voltage moves outside this range, the
POK output is pulled to ground. There is a 30µs
deglitch time when the POK output change its
state.
Bootstrap (BST PIN)
The gatedriver voltage for the high-side N-
channel DMOS power switch is supplied by a
bootstrap capacitor connected between the BS
and SW pins. When the low-side switch is on, the
capacitor is charged through an internal boost
diode. When the high-side switch is on and the
low-side switch turns off, the voltage on the
bootstrap capacitor is boosted above the input
voltage and the internal bootstrap diode prevents
the capacitor from discharging.
.
MP28115 – 4A, 1.5MHz SYNCHRONOUS STEP-DOWN CONVERTER
MP28115 Rev. 0.92 www.MonolithicPower.com 8
1/6/2016 MPS Proprietary Information. Patent Protected.
Unauthorized Photocopy and Duplication Prohibited.
© 2016 MPS. All Rights Reserved.
APPLICATION INFORMATION
Output Voltage Setting
The external resistor divider sets the output
voltage (see Page 1). The feedback resistor R1
also sets the feedback loop bandwidth with the
internal compensation (refer to description
function). The relation between R1 and feedback
loop bandwidth (f
C
), output capacitance (C
O
) is as
following:
6
CO
1.24 10
R1(K )
f(KHz) C(uF)
×
Ω=
×
The feedback loop bandwidth (f
C
) is no higher
than 1/10 of switching frequency of MP2119. In
the case of ceramic capacitor as C
O
, it’s usually
set to be in the range of 50 kHz and 150 kHz for
optimal transient performance and good phase
margin. If electrolytic capacitor is used, the loop
bandwidth is no higher than 1/4 of the ESR zero
frequency (f
ESR
). f
ESR
is given by:
ESR
ESR O
1
f
2R C
=
π× ×
For example, choose f
C
=70 kHz with ceramic
capacitor, C
O
=47uF, R1 is estimated to be 400k.
R2 is then given by:
OUT
R1
R2 =
V
-1
0.8V
Table 1—Resistor Selection vs. Output
Voltage Setting
V
OUT
(V)
R1
(k)
R2
(k)
L
(H)
C
OUT
(ceramic)
1.2 400 806 0.47μH-1μH 47μF
1.5 400 453 0.47μH-1μH 47μF
1.8 400 316 0.47μH-1μH 47μF
2.5 400 187 0.47μH-1μH 47μF
3.3 400 127 0.47μH-1μH 47μF
Inductor Selection
A 0.47µH to 1µH inductor with DC current rating
at least 25% higher than the maximum load
current is recommended for most applications.
For best efficiency, the inductor DC resistance
shall be <10m. See Table 2 for recommended
inductors and manufacturers. For most designs,
the inductance value can be derived from the
following equation:
OUT IN OUT
IN L OSC
Vx(V-V)
L=
VxΔIxf
where IL is Inductor Ripple Current. Choose
inductor ripple current approximately 30% of the
maximum load current, 4A.
The maximum inductor peak current is:
L
L(MAX) LOAD
ΔI
I=I+
2
Under light load conditions, larger inductance is
recommended for improved efficiency.
Input Capacitor Selection
The input capacitor reduces the surge current
drawn from the input and the switching noise
from the device. The input capacitor impedance
at the switching frequency shall be less than
input source impedance to prevent high
frequency switching current passing to the input
source. Ceramic capacitors with X5R or X7R
dielectrics are highly recommended because of
their low ESR and small temperature coefficients.
For most applications, a 47µF capacitor is
sufficient.
Table 2—Suggested Surface Mount Inductors
Manufacturer
Part
Number
Inductan
ce
(H)
Max DCR
(m)
Current Rating
(A)
Dimensions
L x W x H (mm3)
Wurth Electronics
744310055 0.55 4.5 14 7×6.9×3
744310095 0.95 7.4 11 7×6.9×3
TOKO
B1015AS-1R0N 1 11 6.9 8.4×8.3×4
MP28115 – 4A, 1.5MHz SYNCHRONOUS STEP-DOWN CONVERTER
MP28115 Rev. 0.92 www.MonolithicPower.com 9
1/6/2016 MPS Proprietary Information. Patent Protected.
Unauthorized Photocopy and Duplication Prohibited.
© 2016 MPS. All Rights Reserved.
Output Capacitor Selection
The output capacitor keeps output voltage ripple
small and ensures a stable regulation loop. The
output capacitor impedance shall be low at the
switching frequency. Ceramic capacitors with
X5R or X7R dielectrics are recommended. The
output ripple V
OUT is approximately:
Δ≤
OUT IN OUT
OUT
IN OSC OSC 3
Vx(V-V) 1
V x(ESR + )
V xf xL 8xf xC
External Schottky Diode
For this part, an external schottky diode is
recommended to be placed close to "SW" and
"GND" pins, especially when the output current is
larger than 2A.
With the external schottky diode, the voltage
spike and negative kick on "SW" pin can be
minimized; moreover, the conversion efficiency
can also be improved a little.
For the external schottky diode selection, it's
noteworthy that the maximum reverse voltage
rating of the external diode should be larger than
the maximum input voltage. As for the current
rating of this diode, 0.5A rating should be
sufficient.
PCB Layout Guide
PCB layout is very important to achieve stable
operation. It is highly recommended to duplicate
EVB layout for optimum performance. If change
is necessary, please follow these guidelines as
follows. Here, the typical application circuit is
taken as an example to illustrate the key layout
rules should be followed.
1) For MP28115, a PCB layout with more than
(or) four layers is recommended.
2) The high current paths (GND, IN and SW)
should be placed very close to the device with
short, direct and wide traces.
3) For MP28115, two input ceramic capacitors
(2 x (10μF~22μF)) are strongly recommended to
be placed on both sides of the MP28115
package and keep them as close as possible to
the “IN” and “GND” pins. If this placement is not
possible, a ceramic cap (10μF~47μF) must be
placed across PIN7-“IN”and PIN9-“GND” since
the internal Vcc supply is powered from PIN7,
and good decoupling is needed to avoid any
interference issues.
4) The external feedback resistors shall be
placed next to the FB pin. Keep the FB trace as
short as possible. Don’t place test points on FB
trace if possible.
5) Keep the switching node SW short and away
from the feedback network.

MP28115DQ-LF-Z

Mfr. #:
Manufacturer:
Monolithic Power Systems (MPS)
Description:
Switching Voltage Regulators 4A, 6V, 1.5MHz Synch Step-Down
Lifecycle:
New from this manufacturer.
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