11
LTC1321/LTC1322/LTC1335
Figure 6. Receiver Output
Enable/Disable Timing Test Load
Figure 5. EIA/TIA-562 Receiver
Timing Test Circuit
Figure 4. EIA/TIA-562 Driver
Timing Test Circuit
TEST CIRCUITS
Figure 3. RS485 Driver Output
Enable/Disable Timing Test Load
Figure 2. RS485 Driver/Receiver
Timing Test Circuit
Figure 1. RS485 Driver
Test Load
R
R
V
OD
Y
Z
1321/22/35 F01
V
OC
DR OUT
C
L
500Ω
S2
1321/22/35 F03
V
CC
S1
R
L
1321/22/35 F04
Y OR Z
0V
SEL
D
C
L
RX OUT
C
L
1k
S2
1321/22/35 F06
V
CC
S1
R
L
C
L
1321/22/35 F02
Y
3V
3V
SEL
DE
Z
C
L
A
SEL
3V
0V
R
B
15pF
D
OE
1321/22/35 F05
15pF
Y OR Z
0V
SEL
D
R
0V
SEL
A OR B
0V
OE
R
A1
PORT 1 = EIA562 MODE
PORT 2 = EIA562 MODE
23
D
Y2
17
14
R
B2
PORT 1 = RS485 MODE
PORT 2 = RS485 MODE
D
Y1
5
6
V
CC
ON
DE1
Z1
Y1
PORT 1 = RS485 MODE
PORT 2 = EIA562 MODE
D
Z2
Y2
Z2
SEL2
24
4
7
8
9
22
21
20
LB
18
19
16
GND
V
EE
12
13
R
A2
15
PORT 1 = EIA562 MODE
PORT 2 = RS485 MODE
1
*V
DD
/OE
*
R
B1
R
B1
R
A1
V
CC
D
Z1
D
Y1
ON
Z1
D
Y2
D
Z2
Z2
Y2
SEL1
SEL2
23
24
1
4
6
7
8
9
21
22
19
LB
18
17
GND
V
EE
15
14
13
R
A2
R
B2
16
Y1
5
20
*V
DD
/OE
*
12
R
B1
R
A1
V
CC
D
Z1
D
Y1
ON
Z1
D
Y2
DE2
Z2
Y2
SEL1
23
24
1
4
6
7
8
9
21
22
19
LB
18
17
GND
V
EE
15
14
13
R
A2
R
B2
16
Y1
5
20
*V
DD
/OE
*
12
R
A1
V
CC
DE1
D
Y1
ON
Z1
D
Y2
DE2
Z2
Y2
23
24
1
4
6
7
8
9
21
22
19
LB
18
17
GND
V
EE
15
14
13
R
A2
R
B2
16
Y1
5
20
*V
DD
/OE
*
R
B1
1322/35 BD02
12
**SEL1
**SEL2
**SEL2
**SEL1
FOR LTC1322 ONLY, PIN 1 IS V
DD
, AND OE IS ALWAYS ENABLED.
FOR LTC1335, PIN 1 IS OE, AND V
DD
IS CONNECTED TO V
CC
.
SEL1/SEL2 = V
CC
.
*
**
LTC1322/LTC1335 Interface Configuration With Loopback
BLOCK DIAGRA SM
W
