MAX17006AETP+T Datasheet MAX17006AETP+T, MAX17015AETP+, MAX17015AETP+T | P16-P18

MAX17005A/MAX17006A/MAX17015A

1.2MHz, Low-Cost,

High-Performance Chargers

16 ______________________________________________________________________________________

CC, CCI, CCS, and LVC Control Blocks

The MAX17005A/MAX17006A/MAX17015A control

input current (CCS control loop), charge current (CCI

control loop), or charge voltage (CC control loop),

depending on the operating condition. The three con-

trol loops, CC, CCI, and CCS are brought together

internally at the lowest voltage clamp (LVC) amplifier.

The output of the LVC amplifier is the feedback control

signal for the DC-DC controller. The minimum voltage

at the CC, CCI, or CCS appears at the output of the

LVC amplifier and clamps the other control loops to

within 0.3V above the control point. Clamping the other

two control loops close to the lowest control loop

ensures fast transition with minimal overshoot when

switching between different control loops (see the

Compensation

section). The CCS and CCI loops are

compensated internally, and the CC loop is compen-

sated externally.

Continuous-Conduction Mode

With sufficiently large charge current, the MAX17005A/

MAX17006A/MAX17015s’ inductor current never cross-

es zero, which is defined as continuous-conduction

mode. The controller starts a new cycle by turning on

the high-side MOSFET and turning off the low-side

MOSFET. When the charge-current feedback signal

(CSI) is greater than the control point (LVC), the CCMP

comparator output goes high and the controller initiates

the off-time by turning off the high-side MOSFET and

turning on the low-side MOSFET. The operating fre-

quency is governed by the off-time and is dependent

upon V

CSIN

and V

DCIN

The on-time can be determined using the following

equation:

where:

The switching frequency can then be calculated:

At the end of the computed off-time, the controller initi-

ates a new cycle if the control point (LVC) is greater

than 10mV (V

CSIP

- V

CSIN

referred), and the charge

current is less than the cycle-by-cycle current limit.

Restated another way, IMIN must be high, IMAX must

be low, and OVP must be low for the controller to initi-

ate a new cycle. If the peak inductor current exceeds

IMAX comparator threshold or the output voltage

exceeds the OVP threshold, then the on-time is termi-

nated. The cycle-by-cycle current limit effectively pro-

tects against overcurrent and short-circuit faults.

If during the off-time the inductor current goes to zero,

the ZCMP comparator output pulls high, turning off the

low-side MOSFET. Both the high- and low-side

MOSFETs are turned off until another cycle is ready to

begin. ZCOMP causes the MAX17005A/MAX17006A/

MAX17015A to enter into the discontinuous conduction

mode (see the

Discontinuous Conduction

section).

Discontinuous Conduction

The MAX17005A/MAX17006A/MAX17015A can also

operate in discontinuous conduction mode to ensure that

the inductor current is always positive. The MAX17005A/

MAX17006A/MAX17015A enter discontinuous conduction

mode when the output of the LVC control point falls below

10mV (referred at V

CSIP

- V

CSIN

). For RS2 = 10mΩ, this

corresponds to a peak inductor current of 1A.

In discontinuous mode, a new cycle is not started until

the LVC voltage rises above IMIN. Discontinuous mode

operation can occur during conditioning charge of

overdischarged battery packs, when the charge cur-

rent has been reduced sufficiently by the CCS control

loop, or when the charger is in constant-voltage mode

with a nearly full battery pack.

Compensation

The charge voltage, charge current, and input current-

limit regulation loops are compensated separately. The

charge current and input current-limit loops, CCI and

CCS, are compensated internally, whereas the charge

voltage loop is compensated externally at CC.

ON OFF

RIPPLE

BATT OFF

RIPPLE

DCIN BATT

MAX17005A/MAX17006A/MAX17015A

1.2MHz, Low-Cost,

High-Performance Chargers

______________________________________________________________________________________ 17

CC Loop Compensation

The simplified schematic in Figure 7 is sufficient to

describe the operation of the controller’s voltage loop,

CC. The required compensation network is a pole-zero

pair formed with C

and R

. The zero is necessary

to compensate the pole formed by the output capacitor

and the load. R

ESR

is the equivalent series resistance

(ESR) of the charger output capacitor (C

OUT

). R

is the

equivalent charger output load, where R

= ΔV

BATT

ΔI

CHG

. The equivalent output impedance of the GMV

amplifier, R

OGMV

, is greater than 10MΩ. The voltage-

amplifier transconductance, GMV = 0.125μA/mV. The

DC-DC converter transconductance is dependent upon

charge current-sense resistor RS2:

where A

CSI

= 20, and RS2 = 10mΩ in the typical appli-

cation circuits, so GM

OUT

= 5A/V.

The loop transfer function is given by:

The poles and zeros of the voltage-loop transfer function

are listed from lowest frequency to highest frequency in

Table 2.

Near crossover, C

is much lower impedance than

OGMV

. Since C

is in parallel with R

OGMV,

domi-

nates the parallel impedance near crossover. Additionally,

is much higher impedance than C

and dominates

the series combination of R

and C

, so:

OUT

is also much lower impedance than R

near

crossover so the parallel impedance is mostly capaci-

tive and:

sC R sC

OUT L OUT

()1

+×

≅

RsCR

sC R

OGMV CC CC

CC OGMV

×+ ×

+×

≅

()

LTF R GMV R

sC R

=×××

+×

OUT L OGMV

OUT ESR

(1 ))( )

()()

+×

+× + ×

sC R

sC R sC R

CC CC

CC OGMV OUT L

GM =

OUT

2ARS

CSI ×

NAME EQUATION DESCRIPTION

CCV Pole Lowest frequency pole created by C

and GMV’s finite output resistance.

CCV Zero

Voltage-loop compensation zero. If this zero is at the same frequency or lower

than output pole f

P_OUT

, the loop-transfer function approximates a single-pole

response near the crossover frequency. Choose C

to place this zero at

least one decade below crossover to ensure adequate phase margin.

Output

Pole

Output pole formed with the effective load resistance R

and the output

capacitance C

OUT

. R

influences the DC gain but does not affect the stability

of the system or the crossover frequency.

Output

Zero

Output ESR Zero. This zero can keep the loop from crossing unity gain if

Z_OUT

is less than the desired crossover frequency; therefore, choose a

capacitor with an ESR zero greater than the crossover frequency.

Table 2. CC Loop Poles and Zeros

PCV

OGMV CC

2π

ZCV

CC CC

2π

POUT

LOUT

2π

ZOUT

ESR OUT

2π

OUT

BATT

ESR

OUT

VCTL

OGMV

GMV

Figure 7. CC Loop Diagram

MAX17005A/MAX17006A/MAX17015A

1.2MHz, Low-Cost,

High-Performance Chargers

18 ______________________________________________________________________________________

If R

ESR

is small enough, its associated output zero has

a negligible effect near crossover and the loop-transfer-

function can be simplified as follows:

Setting LTF = 1 to solve for the unity-gain frequency

yields:

For stability, choose a crossover frequency lower than

1/10 the switching frequency (f

OSC)

. For example,

choose a crossover frequency of 50kHz and solve for

using the component values listed in Figure 1 to

yield R

= 3kΩ:

GMV = 0.125μA/mV

OUT

= 5A/V

OUT

= 4.7μF

OSC

= 600kHz

= 0.2Ω

CO_CV

= 50kHz

To ensure that the compensation zero adequately can-

cels the output pole, select f

Z_CV

≤ f

P_OUT

≥ (R

) x C

OUT

≥ 300pF (assuming 2 cells and 2A maximum

charge current).

Figure 8 shows the Bode plot of the voltage-loop-

frequency response using the values calculated above.

MOSFET Drivers

The DHI and DLO outputs are optimized for driving

moderate-sized power MOSFETs. The MOSFET drive

capability is the same for both the low-side and high-

sides switches. This is consistent with the variable duty

factor that occurs in the notebook computer environ-

ment where the battery voltage changes over a wide

range. There must be a low-resistance, low-inductance

path from the DLO driver to the MOSFET gate to pre-

vent shoot-through. Otherwise, the sense circuitry in the

MAX17005A/MAX17006A interpret the MOSFET gate as

“off” while there is still charge left on the gate. Use very

short, wide traces measuring 10 to 20 squares or fewer

(1.25mm to 2.5mm wide if the MOSFET is 25mm from

the device). Unlike the DLO output, the DHI output uses

a 50ns (typ) delay time to prevent the low-side MOSFET

from turning on until DHI is fully off. The same consider-

ations should be used for routing the DHI signal to the

high-side MOSFET.

The high-side driver (DHI) swings from LX to 5V above

LX (BST) and has a typical impedance of 1.5Ω sourcing

and 0.8Ω sinking. The strong high-side MOSFET driver

eliminates most of the power dissipation due to switch-

ing losses. The low-side driver (DLO) swings from LDO

to ground and has a typical impedance of 3Ω sinking

and 3Ω sourcing. This helps prevent DLO from being

pulled up when the high-side switch turns on due to

capacitive coupling from the drain to the gate of the

low-side MOSFET. This places some restrictions on the

MOSFETs that can be used. Using a low-side

MOSFET with smaller gate-to-drain capacitance can

prevent these problems.

Design Procedure

MOSFET Selection

Choose the n-channel MOSFETs according to the maxi-

mum required charge current. The MOSFETs must be

able to dissipate the resistive losses plus the switching

losses at both V

DCIN(MIN)

and V

DCIN(MAX)

For the high-side MOSFET, the worst-case resistive

power losses occur at the maximum battery voltage

and minimum supply voltage:

PD High Side

COND

BATT MAX

DCIN MIN

CHG

()

=×

×× R

DS ON()

GMV GM

OUT CO CV

OUT

≅

×2

fGMG

CO CV OUT MV

OUT

=××

×2π

LTF GM

OUT

=×

FREQUENCY (Hz)

MAGNITUDE (dB)

PHASE (DEGREES)

100k10k1k100101

-20

-40

-90

-45

-135

0.1 1M

MAG

PHASE

Figure 8. CC Loop Response

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MAX17006AETP+T

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Battery Management

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MAX17006AETP+T

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