LTC2704
16
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should be driven with a Thevenin-equivalent impedance
of 10k or less. If not used, they should be shorted to
their respective signal grounds, AGNDx.
POWER-ON RESET AND CLEAR
When power is fi rst applied to the LTC2704, all DACs
power-up in 5V unipolar mode (S3 S2 S1 S0 = 0000). All
internal DAC registers are reset to 0 and the DAC outputs
are zero volts.
When the CLR pin is taken low, a system clear results. The
command and address shift registers, and the code and
confi guration B2 buffers, are reset to 0; the DAC outputs
are all reset to zero volts. The B1 buffers are left intact, so
that any subsequent “Update B1B2” command (includ-
ing the use of LDAC) restores the addressed DACs to their
respective previous states.
If CLR is asserted during an operation, i.e., when CS/LD
is low, the operation is aborted. Integrity of the relevant
input (B1) buffers is not guaranteed under these condi-
tions, therefore the contents should be checked using
readback or replaced.
The RFLAG pin is used as a fl ag to notify the system of a
loss of data integrity. The RFLAG output is asserted low
at power-up, system clear, or if the logic supply V
DD
dips
below approximately 2V; and stays asserted until any valid
update command is executed.
SLEEP MODE
When a sleep command (C3 C2 C1 C0 = 1110) is issued,
the addressed DAC or DACs go into power-down mode.
DACs A and B share a reference inverting amplifi er as do
DACs C and D. If either DAC A or DAC B (similarly for DACs
C and D) is powered down, its shared reference inverting
amplifi er remains powered on. When both DAC A and DAC B
are powered down together, their shared reference invert-
ing amplifi er is also powered down (similarly for DACs C
and D). To determine the sleep status of a particular DAC,
a direct read span command is performed by addressing
the DAC and reading its status on the readback pin SRO.
The fi fth LSB is the sleep status bit (see Figures 2a and
2b). Table 4 shows the sleep status bit’s functionality.
Table 4. Readback Sleep Status Bit
SLP STATUS
0 DAC n Awake
1 DAC n in Sleep Mode
OPERATION
LTC2704
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APPLICATIONS INFORMATION
Overview
The LTC2704 is a highly integrated device, greatly sim-
plifying design and layout as compared to a design using
multiple current output DACs and separate amplifi ers. A
similar design using four separate current output DACs
would require six precision op amps, compensation capaci-
tors, bypass capacitors for each amplifi er, several times as
much PCB area and a more complicated serial interface.
Still, it is important to avoid some common mistakes in
order to achieve full performance. DC752A is the evalu-
ation board for the LTC2704. It is designed to meet all
data sheet specifi cations, and to allow the LTC2704 to be
integrated into other prototype circuitry. All force/sense
lines are available to allow the addition of current booster
stages or other output circuits.
The DC752A design is presented as a tutorial on properly
applying the LTC2704. This board shows how to properly
return digital and analog ground currents, and how to
compensate for small differences in ground potential
between the two banks of two DACs. There are other ways
to ground the LTC2704, but the one requirement is that
analog and digital grounds be connected at the LTC2704
by a very low impedance path. It is NOT advisable to split
the ground planes and connect them with a jumper or
inductor. When in doubt, use a single solid ground plane
rather than separate planes.
The LTC2704 does allow the ground potential of the DACs
to vary by ±300mV with respect to analog ground, allowing
compensation for ground return resistance.
Power Supply Grounding and Noise
LTC2704 V
+
and V
pins are the supplies to all of the
output amplifi ers, ground sense amplifi ers and reference
inversion amplifi ers. These amplifi ers have good power
supply rejection, but the V
+
and V
supplies must be free
from wideband noise. The best scheme is to prefi lter low
noise regulators such as the LT
®
1761 (positive) and LT1964
(negative). Refer to Linear Technology Application Note
101, Minimizing Switching Regulator Residue in Linear
Regulator Outputs.
The LTC2704 V
DD
pin is the supply for the digital logic
and analog DAC switches and is very sensitive to noise. It
must be treated as an analog supply. The evaluation board
uses an LT1790 precision reference as the V
DD
supply to
minimize noise.
The GND pin is the return for digital currents and the
AGND pin is a bias point for internal analog circuitry. Both
of these pins must be tied to the same point on a quiet
ground plane.
Each DAC has a separate ground sense pin that can be used
to compensate for small differences in ground potential
within a system. Since DACs A and B are associated with
REF1 and DACs C and D are associated with REF2, the
grounds must be grouped together as follows:
AGNDA, AGNDB and REFG1 tied together (“GND1” on
DC752A)
AGNDC, AGNDD and REFG2 tied together (“GND2” on
DC752A)
This scheme allows compensation for ground return IR
drops, as long as the resistance is shared by both DACs
in a group. This implies that the ground return for DACs
A and B must be as close as possible, and GND1 must
be connected to this point through a low current, low
resistance trace. (Similar for DACs C and D.)
Figure 3 shows the top layer of the evaluation board. The
GND1 trace connects REFG1, AGNDA, AGNDB and the
ground pin of the LT1236 precision reference (U4.) This
point is the ground reference for DACs A and B. The GND2
trace connects REFG2, AGNDC, AGNDD and the ground pin
of the other LT1236 precision reference (U5). This point
is the ground reference for DACs C and D.
Voltage Reference
A high quality, low noise reference such as the LT1236
or LT1027 must be used to achieve full performance.
The ground terminal of this reference must be connected
directly to the common ground point. If GND1 and GND2
are separate, then two references must be used.
LTC2704
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Voltage Output/Feedback and Compensation
The LTC2704 provides separate voltage output and feedback
pins for each DAC. This allows compensation for resistance
between the output and load, or a current boosting stage
such as an LT1970 may be inserted without affecting ac-
curacy. When OUTx is connected directly to RFBx and no
GND1 TRACE,
SEPARATED FROM
AGND UNDER LTC2704
EXPOSED GROUND PLANE AROUND EDGE
ALLOWS GROUNDING TO PROTOTYPE CIRCUITS
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GND2 TRACE,
SEPARATED FROM
AGND UNDER LTC2704
CUTOUT PREVENTS DIGITAL RETURN CURRENTS
FROM COUPLING INTO ANALOG GROUND PLANE. NOTE
THAT THERE IS A PLANE IN THIS REGION ON LAYER 3
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Figure 3. DC752 Top Layer
Figure 4. DC752 Analog Ground Layer. No Currents Are Returned
to this Plane, so it May Be Used As a Reference Point for Precise
Voltage Measurements
additional capacitance is present, the internal frequency
compensation is suffi cient for stability and is optimized
for fast settling time. If a low bandwidth booster stage is
used, then a compensation capacitor from OUTx to C1x
may be required. Similarly, extra compensation may be
required to drive a heavy capacitive load.
APPLICATIONS INFORMATION

LTC2704IGW-14#TRPBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Digital to Analog Converters - DAC Quad 14-bit, SPI SoftSpan Vout DAC
Lifecycle:
New from this manufacturer.
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