1
Features
Fast Read Access Time – 90 ns
5-volt Only Reprogramming
Sector Program Operation
Single Cycle Reprogram (Erase and Program)
2048 Sectors (256 Bytes/Sector)
Internal Address and Data Latches for 256 Bytes
Internal Program Control and Timer
Hardware and Software Data Protection
Two 16K Bytes Boot Blocks with Lockout
FastSectorProgramCycleTime–10ms
DATA Polling for End of Program Detection
Low Power Dissipation
40mAActiveCurrent
100 µA CMOS Standby Current
Typical Endurance > 10,000 Cycles
Single 5V ± 10% Supply
CMOS and TTL Compatible Inputs and Outputs
Description
The AT29C040A is a 5-volt only in-system Flash Programmable and Erasable Read
Only Memory (PEROM). Its 4 megabits of memory is organized as 524,288 words by
8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS EEPROM technology,
the device offers access times up to 90 ns, and a low 220 mW power dissipation.
When the device is deselected, the CMOS standby current is less than 100 µA. The
device endurance is such that any sector can typically be written to in excess of
10,000 times. The programming algorithm is compatible with other devices in Atmel’s
5-volt only Flash family.
4-megabit
(512K x 8)
5-volt Only
256-byte Sector
Flash Memory
AT29C040A
Rev. 0333I–FLASH–05/02
DIP Top View
Pin Configurations
Pin Name Function
A0 - A18 Addresses
CE
Chip Enable
OE
Output Enable
WE
Write Enable
I/O0 - I/O7 Data Inputs/Outputs
NC No Connect
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A18
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
VCC
WE
A17
A14
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
PLCC Top View
TSOP Top View Type 1
5
6
7
8
9
10
11
12
13
29
28
27
26
25
24
23
22
21
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
A14
A13
A8
A9
A11
OE
A10
CE
I/O7
4
3
2
1
32
31
30
14
15
16
17
18
19
20
I/O1
I/O2
GND
I/O3
I/O4
I/O5
I/O6
A12
A15
A16
A18
VCC
WE
A17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A11
A9
A8
A13
A14
A17
WE
VCC
A18
A16
A15
A12
A7
A6
A5
A4
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3
2
AT29C040A
0333IFLASH05/02
To allow for simple in-system reprogrammability, the AT29C040A does not require high input
voltages for programming. Five-volt-only commands determine the operation of the device.
Reading data out of the device is similar to reading from an EPROM. Reprogramming the
AT29C040A is performed on a sector basis; 256 bytes of data are loaded into the device and
then simultaneously programmed.
During a reprogram cycle, the address locations and 256 bytes of data are internally latched,
freeing the address and data bus for other operations. Following the initiation of a program
cycle, the device will automatically erase the sector and then program the latched data using
an internal control timer. The end of a program cycle can be detected by DATA
polling of I/O7.
Once the end of a program cycle has been detected, a new access for a read or program can
begin.
Block Diagram
Device
Operation
READ: The AT29C040A is accessed like an EPROM. When CE and OE are low and WE is
high, the data stored at the memory location determined by the address pins is asserted on
the outputs. The outputs are put in the high impedance state whenever CE
or OE is high. This
dual-line control gives designers flexibility in preventing bus contention.
BYTE LOAD: Byte loads are used to enter the 256 bytes of a sector to be programmed or
the software codes for data protection. A byte load is performed by applying a low pulse on the
WE
or CE input with CE or WE low (respectively) and OE high. The address is latched on the
falling edge of CE
or WE, whichever occurs last. The data is latched by the first rising edge of
CE
or WE.
PROGRAM: The device is reprogrammed on a sector basis. If a byte of data within a sector
is to be changed, data for the entire sector must be loaded into the device. Any byte that is not
loaded during the programming of its sector will be erased to read FFH. Once the bytes of a
sector are loaded into the device, they are simultaneously programmed during the internal
programming period. After the first data byte has been loaded into the device, successive
bytes are entered in the same manner. Each new byte to be programmed must have its high
to low transition on WE
(or CE) within 150 µs of the low to high transition of WE (or CE)ofthe
preceding byte. If a high to low transition is not detected within 150 µs of the last low to high
transition, the load period will end and the internal programming period will start. A8 to A18
specify the sector address. The sector address must be valid during each high to low transition
of WE
(or CE). A0 to A7 specify the byte address within the sector. The bytes may be loaded
in any order; sequential loading is not required. Once a programming operation has been initi-
ated, and for the duration of t
WC
, a read operation will effectively be a polling operation.
3
AT29C040A
0333IFLASH05/02
SOFTWARE DATA PROTECTION: A software controlled data protection feature is avail-
able on the AT29C040A. Once the software protection is enabled a software algorithm must
be issued to the device before a program may be performed. The software protection feature
may be enabled or disabled by the user; when shipped from Atmel, the software data protec-
tion feature is disabled. To enable the software data protection, a series of three program
commands to specific addresses with specific data must be performed. After the software data
protection is enabled the same three program commands must begin each program cycle in
order for the programs to occur. All software program commands must obey the sector pro-
gram timing specifications. The SDP feature protects all sectors, not just a single sector. Once
set, the software data protection feature remains active unless its disable command is issued.
Power transitions will not reset the software data protection feature, however the software fea-
ture will guard against inadvertent program cycles during power transitions.
After setting SDP, any attempt to write to the device without the three-byte command
sequence will start the internal write timers. No data will be written to the device; however, for
the duration of t
WC
, a read operation will effectively be a polling operation.
After the software data protections 3-byte command code is given, a byte load is performed
by applying a low pulse on the WE
or CE input with CE or WE low (respectively) and OE high.
The address is latched on the falling edge of CE
or WE, whichever occurs last. The data is
latched by the first rising edge of CE
or WE. The 256 bytes of data must be loaded into each
sector by the same procedure as outlined in the program section under device operation.
HARDWARE DATA PROTECTION: Hardware features protect against inadvertent pro-
grams to the AT29C040A in the following ways: (a) V
CC
sense if V
CC
is below 3.8V (typical),
the program function is inhibited; (b) V
CC
power on delay once V
CC
has reached the V
CC
sense level, the device will automatically time out 5 ms (typical) before programming; (c) Pro-
gram inhibit holding any one of OE
low, CE high or WE high inhibits program cycles; and (d)
Noise filter pulses of less than 15 ns (typical) on the WE
or CE inputs will not initiate a pro-
gram cycle.
PRODUCT IDENTIFICATION: The product identification mode identifies the device and
manufacturer as Atmel. It may be accessed by hardware or software operation. The hardware
operation mode can be used by an external programmer to identify the correct programming
algorithm for the Atmel product. In addition, users may wish to use the software product identi-
fication mode to identify the part (i.e. using the device code), and have the system software
use the appropriate sector size for program operations. In this manner, the user can have a
common board design for 256K to 4-megabit densities and, with each densityssectorsizein
a memory map, have the system software apply the appropriate sector size.
For details, see Operating Modes (for hardware operation) or Software Product Identification.
The manufacturer and device code is the same for both modes.
DATA
POLLING: The AT29C040A features DATA polling to indicate the end of a program
cycle. During a program cycle an attempted read of the last byte loaded will result in the com-
plement of the loaded data on I/O7. Once the program cycle has been completed, true data is
valid on all outputs and the next cycle may begin. DATA
polling may begin at any time during
the program cycle.
TOGGLE BIT: In addition to DATA
polling the AT29C040A provides another method for
determining the end of a program or erase cycle. During a program or erase operation, suc-
cessive attempts to read data from the device will result in I/O6 toggling between one and
zero. Once the program cycle has completed, I/O6 will stop toggling and valid data will be
read. Examining the toggle bit may begin at any time during a program cycle.
OPTIONAL CHIP ERASE MODE: The entire device can be erased by using a 6-byte soft-
ware code. Please see Software Chip Erase application note for details.

AT29C040A-12TI

Mfr. #:
Manufacturer:
Microchip Technology / Atmel
Description:
NOR Flash 4M (512kx8)
Lifecycle:
New from this manufacturer.
Delivery:
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Payment:
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