HIGH RIPPLE-REJECTION LOW DROPOUT CMOS VOLTAGE REGULATOR
Rev.3.0_00
S-T111 Series
Seiko Instruments Inc.
7
Test Circuits
1.
VSS
VOUT
ON/OFF
Set to
power ON
VIN
V
A
+
+
Figure 4
2.
VSS
VOUT
ON/OFF
Set to
V
IN
or GND
VIN
A
Figure 5
3.
Set to
power ON
VSS
VOUT
ON/OFF
VIN
V
A
+
+
Figure 6
4.
VSS
VOUT
ON/OFF
VIN
A
V
R
L
+ +
Figure 7
5.
VSS
VOUT
ON/OFF
VIN
V
+
Set to
Power ON
R
L
Figure 8
HIGH RIPPLE-REJECTION LOW DROPOUT CMOS VOLTAGE REGULATOR
S-T111 Series
Rev.3.0_00
Seiko Instruments Inc.
8
Standard Circuit
ON/OFF
VSS
VOUTVIN
C
IN
*1
C
L
*2
Input
Output
GND
Single GND
*1. C
IN
is a capacitor for stabilizing the input.
*2. A ceramic capacitor of 0.1 μF or more can be used for C
L
.
Figure 9
Caution The above connection diagram and constant will not guarantee successful operation.
Perform thorough evaluation using the actual application to set the constant.
Application Conditions
Input capacitor (C
IN
): 0.1 μF or more
Output capacitor (C
L
): 0.1 μF or more
ESR of output capacitor: 10 Ω or less
Caution A general series regulator may oscillate, depending on the external components selected.
Check that no oscillation occurs with the application using the above capacitor.
Selection of Input and Output Capacitors (C
IN
, C
L
)
The S-T111 Series requires an output capacitor between the VOUT and VSS pins for phase compensation.
Operation is stabilized by a ceramic capacitor with an output capacitance of 0.1 μF or more in the entire
temperature range. However, when using an OS capacitor, tantalum capacitor, or aluminum electrolytic
capacitor, a ceramic capacitor with a capacitance of 0.1 μF or more and an ESR of 10 Ω or less is required.
The value of the output overshoot or undershoot transient response varies depending on the value of the output
capacitor. The required capacitance of the input capacitor differs depending on the application.
The recommended value for an application is 1.0 μF or more for C
IN
and 0.47 μF or more for C
L
; however,
when selecting the output capacitor, perform sufficient evaluation, including evaluation of temperature
characteristics, on the actual device.
HIGH RIPPLE-REJECTION LOW DROPOUT CMOS VOLTAGE REGULATOR
Rev.3.0_00
S-T111 Series
Seiko Instruments Inc.
9
Explanation of Terms
1. Low dropout voltage regulator
The low dropout voltage regulator is a voltage regulator whose dropout voltage is low due to its built-in
low on-resistance transistor.
2. Low ESR
A capacitor whose ESR (Equivalent Series Resistance) is low. The S-T111 Series enables use of a low
ESR capacitor, such as a ceramic capacitor, for the output-side capacitor C
L
. A capacitor whose ESR is
10 Ω or less can be used.
3. Output voltage (V
OUT
)
The accuracy of the output voltage is ensured at ±1.0% under the specified conditions of fixed input
voltage
*1
, fixed output current, and fixed temperature.
*1. Differs depending on the product.
Caution If the above conditions change, the output voltage value may vary and exceed the
accuracy range of the output voltage. Please see the “Electrical Characteristics” and
attached characteristics data for details.
4. Line Regulation
OUTIN
OUT1
VΔV
ΔV
Indicates the dependency of the output voltage on the input voltage. That is, the values show how
much the output voltage changes due to a change in the input voltage with the output current remaining
unchanged.
5. Load regulation (ΔV
OUT2
)
Indicates the dependency of the output voltage on the output current. That is, the values show how
much the output voltage changes due to a change in the output current with the input voltage remaining
unchanged.
6. Dropout voltage (V
drop
)
Indicates the difference between the input voltage V
IN1
, which is the input voltage (V
IN
) at the point where
the output voltage has fallen to 98% of the output voltage value V
OUT3
after V
IN
was gradually decreased
from V
IN
= V
OUT(S)
+ 1.0 V, and the output voltage at that point (V
OUT3
× 0.98).
V
drop
= V
IN1
(V
OUT3
× 0.98)

S-T111B27MC-OGMTFG

Mfr. #:
Manufacturer:
ABLIC
Description:
LDO Voltage Regulators VOLTAGE REGULATOR
Lifecycle:
New from this manufacturer.
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