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ST7538QTR

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P44
Functional description ST7538Q
16/44
5.3 Mark and space frequencies
Mark and space communication frequencies are defined by the following formula:
F ("0") = FCarrier + [
∆F]/2
F ("1") = FCarrier - [
∆F]/2
∆F is the Frequency Deviation.
With Deviation = “0.5” the difference in terms of frequency between the mark and space
tones is half the Baudrate value (∆F = 0.5*BAudrate). When the Deviation = “1” the
difference is the Baudrate itself (∆F = Baudrate). The minimal Frequency Deviation is
600Hz.
Table 7. ST7538Q synthesized frequencies
Carrier
Frequency
(KHz)
Baud
Rate
Deviation
Exact
Frequency [Hz]
(Clock=16MHz)
Carrier
Frequen
cy
(KHz)
Baud
Rate
Deviation
Exact
Frequency [Hz]
(Clock=16MHz)
“1” “0” “1” “0”
60 600 -- 82.05 600 --
1 59733 60221 1 81706 82357
1200 0.5 59733 60221 1200 0.5 81706 82357
1 59408 60547 1 81380 82682
2400 0.5 59408 60547 2400 0.5 81380 82682
1 58757 61198 1 80892 83171
4800 0.5 58757 61198 4800 0.5 80892 83171
1 57617 62337 1 79590 84473
66 600 -- 86 600 --
1 65755 66243 1 85775 86263
1200 0.5 65755 66243 1200 0.5 85775 86263
1 65430 66569 1 85449 86589
2400 0.5 65430 66569 2400 0.5 85449 86589
1 64779 67220 1 84798 87240
4800 0.5 64779 67220 4800 0.5 84798 87240
1 63639 68359 1 83659 88379
ST7538Q Functional description
17/44
5.4 ST7538Q mains access
ST7538Q can access the Mains in two different ways:
● Synchronous access
● Asynchronous access
The choice between the two types of access can be performed by means of Control
Register bit 14 (see Ta ble 1 1) and affects the ST7538Q data flow in Transmission Mode as
in Reception Mode (for how to set the communication Mode, see Section 5.5 on page 18).
In Data Transmission Mode:
– Synchronous Mains access: on clock signal provided by ST7538Q (CLR/T line)
rising edge, data transmission line (TxD line) value is read and sent to the FSK
Modulator. ST7538Q manages the Transmission timing according to the
BaudRate Selected.
– Asynchronous Mains access: data transmission line (TxD line) value enters
directly to the FSK Modulator. The Host Controller manages the Transmission
timing (CLR/T line should be neglected).
Carrier
Frequency
(KHz)
Baud
Rate
Deviation
Exact
Frequency [Hz]
(Clock=16MHz)
Carrier
Frequen
cy
(KHz)
Baud
Rate
Deviation
Exact
Frequency [Hz]
(Clock=16MHz)
“1” “0” “1” “0”
72 600 -- 110 600 --
1 71777 72266 1 109701 110352
1200 0.5 71777 72266 1200 0.5 109701 110352
1 71452 72591 1 109375 110677
2400 0.5 71452 72591 2400 0.5 109375 110677
1 70801 73242 1 108724 111165
4800 0.5 70801 73242 4800 0.5 108724 111165
1 69661 74382 1 107585 112467
76 600 -- 132.5 600 --
1 75684 76335 1 132161 132813
1200 0.5 75684 76335 1200 0.5 132161 132813
1 75358 76660 1 131836 133138
2400 0.5 75358 76660 2400 0.5 131836 133138
1 74870 77148 1 131348 133626
4800 0.5 74870 77148 4800 0.5 131348 133626
1 73568 78451 1 130046 134928
Table 7. ST7538Q synthesized frequencies
Functional description ST7538Q
18/44
In Data Reception Mode:
– Synchronous Mains access: on clock signal recovered by a PLL from ST7538Q
(CLR/T line) rising edge, value on FSK Demodulator is read and put to the data
reception line (RxD line). ST7538Q recovers the bit timing according to the
BaudRate Selected.
– Asynchronous Mains access: Value on FSK Demodulator is sent directly to the
data reception line (RxD line). The Host Controller recovers the communication
timing (CLR/T line should be neglected).
5.5 Host processor interface
ST7538Q exchanges data with the host processor through a serial interface.
The data transfer is managed by REG_DATA and RxTx Lines, while data are exchanged
using RxD, TxD and CLR/T lines.
Four are the ST7538Q working modes:
● Data Reception
● Data Transmission
● Control Register Read
● Control Register Write
REG_DATA and RxTx lines are level sensitive inputs.
ST7538Q features two type of Host Communication Interfaces:
–SPI
–UART
The selection can be done through the UART/SPI pin. If UART/SPI pin is forced to “0” SPI
interface is selected while if UART/SPI pin is forced to “1” UART interface is selected
(a)
. The
type of interface affects the Data Reception by setting the idle state of RxD line. When
ST7538Q is in Receiving mode (REG_DATA=”0” and RxTx =“1”) and no data are available
on mains (or RxD is forced to an idle state, i.e. with a conditioned Detection Method), the
RxD line is forced to “0” when UART/SPI pin is forced to ”0” or to “1” when UART/SPI pin is
forced to ”1”.
Table 8. Data and control register access bits configuration
REG_DATA RxTx
Data Transmission 0 0
Data Reception 0 1
Control Register Read 1 1
Control Register Write 1 0
a. UART Interface Mode modifies also Control Register Functions and provides one more level of Rx sensitivity
(see par. 5.11)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P44

ST7538QTR

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Buy ST7538QTR
Manufacturer:
STMicroelectronics
Description:
Network Controller & Processor ICs FSK power line transceiver
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