TRDB_LCM
5
2-2Schematic of the Board
Figure 2.1. Schematic of the TRDB_LCM
TRDB_LCM
6
2-3Pin Description of the 40-pin Interface of TRDB_LCM
The TRDB_LCM has a 40-pin connector. The pin description of the 40-pin
connector follows:
Pin Numbers Name Direction Description
1~10 NC N/A Not connect
11 VCC5 N/A Power 5V
12 GND N/A Ground
13~20 NC N/A Not connect
21 DIN6 Input LCD data bus bit 7
22 DIN7 Input LCD data bus bit 6
23 DIN4 Input LCD data bus bit 4
24 DIN5 Input LCD data bus bit 5
25 DIN2 Input LCD data bus bit 2
26 DIN3 Input LCD data bus bit 3
27 DIN0 Input LCD data bus bit 0
28 DIN1 Input LCD data bus bit 1
29 VCC33 N/A Power 3.3V
30 NC N/A Not connect
31 VSYNC Input Vertical sync input
32 NC N/A Not connect
33 SCL Input 3-wire serial interface clock
34 DCLK Input LCD data clock
35 GRESTB Input Global reset, low active
36 SHDB Input Shutdown control, low active
37 CPW N/A Reserved
38 SCEN Input 3-wire serial interface enable
39 SDA Input/Output 3-wire serial interface data
40 HSYNC Input Horizontal sync input
Digital Panel Design Demonstration
7
Chapter
3
Chapter 3
Digital Panel Design
Demonstration
This chapter illustrates how to exercise the digital panel reference design
provided with the kit. Users can follow the instructions in this chapter to build a 3.6
inch TV player (DE2 user only) and pattern generator using the DE2/DE1 in 5
minutes.
3-1Demonstration Setup
The Demonstration configuration is illustrated as Figure 3.1. The YUV 4:2:2 data
is sent from TV decoder to the cyclone II 2C35 FPGA. The FPGA on the
DE2/DE1 board is handling image processing part and set the LCD module
control register to display on the TRDB_LCM.
Figure 3.1. The TV player Demo configuration setup

P0424

Mfr. #:
Manufacturer:
Terasic Technologies
Description:
Display Development Tools 3.6" LCD Panel Pkg
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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