IDT5V9351PFGI

INDUSTRIAL TEMPERATURE RANGE
4
IDT5V9351
LOW VOLTAGE PLL CLOCK DRIVER
FUNCTION TABLE
(1)
INPUTS OUTPUTS
fSELA fSELB fSELC fSELD QA QB QC QD
0 0 0 0 2 * CLK CLK CLK CLK
0 0 0 1 2 * CLK CLK CLK CLK ÷ 2
0 0 1 0 4 * CLK 2 * CLK CLK 2 * CLK
0 0 1 1 4 * CLK 2 * CLK CLK CLK
0 1 0 0 2 * CLK CLK ÷ 2 CLK CLK
0 1 0 1 2 * CLK CLK ÷ 2 CLK CLK ÷ 2
0 1 1 0 4 * CLK CLK CLK 2 * CLK
0 1 1 1 4 * CLK CLK CLK CLK
1 0 0 0 CLK CLK CLK CLK
1 0 0 1 CLK CLK CLK CLK ÷ 2
1 0 1 0 2 * CLK 2 * CLK CLK 2 * CLK
1 0 1 1 2 * CLK 2 * CLK CLK CLK
1 1 0 0 CLK CLK ÷ 2 CLK CLK
1 1 0 1 CLK CLK ÷ 2 CLK CLK ÷ 2
1 1 1 0 2 * CLK CLK CLK 2 * CLK
1 1 1 1 2 * CLK CLK CLK CLK
NOTE:
1. Output frequency relationship with respect to input reference frequency CLK. QC1 is connected to FBIN.
DC ELECTRICAL CHARACTERISTICS
TA = -40°C to +85°C, VCC = 3.3V ± 5%
Symbol Parameter Test Conditions Min. Typ. Max Unit
VIH Input HIGH Voltage LVCMOS Inputs 2 VCC + 0.3 V
VIL Input LOW Voltage LVCMOS Inputs 0.8 V
VPP Peak-to-Peak Input Voltage PECL_CLK 250 mV
VCMR Common Mode
(1)
PECL_CLK 1 VCC - 0.6 V
VOH Output HIGH Voltage
(2)
IOH = -24mA 2.4 V
V
OL Output LOW Voltage
(2)
IOL = 24mA 0.55 V
IOL = 12mA 0.3
ZOUT Output Impedance 14 - 17 Ω
IIN Input Leakage Current ±150 μA
ICC Maximum Quiescent Supply Current All VCC Pins 1 mA
ICCPLL Maximum PLL Supply Current VCCA Only 3 5 mA
NOTES:
1. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP
(DC) specification.
2. The IDT5V9351 outputs can drive series or paralell terminated 50Ω (or 50Ω to VCC/2) transmission lines on the incident edge.
INDUSTRIAL TEMPERATURE RANGE
IDT5V9351
LOW VOLTAGE PLL CLOCK DRIVER
5
PLL INPUT REFERENCE CHARACTERISTICS
VCC = 3.3V ± 5%, TA = -40°C to +85°C
Symbol Parameter Min. Max Unit
tR, tF TCLK Input Rise/Fall Levels, 0.8V to 2V 1 ns
÷ 2 feedback 100 200
f
REF Reference Input Frequency
(1)
÷ 4 feedback 50 100 M H z
÷ 8 feedback 25 50
Static Test Mode 0 300
f
REFDC Reference Input Duty Cycle 25 75 %
NOTE:
1. Maximum and minimum input reference is limited by the VCO lock range and the feedback divider for the TCLK or PECL_CLK inputs.
AC ELECTRICAL CHARACTERISTICS
(1)
TA = -40°C to +85°C, VCC = 3.3V ± 5%
Symbol Parameter Conditions Min. Typ. Max Unit
tR, tF Output Rise/Fall Time 0.55V to 2.4V 0.1 1 ns
VPP Peak-to-Peak Input Voltage LVPECL 500 1000 mV
VCMR Common Mode Range
(2)
LVPECL 1.2 VCC - 0.9 V
100-200 MHz 45 50 55
tPW Output Duty Cycle 50-100 MHz 47.5 50 52.5 %
25-50 MHz 48.75 50 51.75
tSK(O) Output to Output Skew 150 ps
fVCO PLL VCO Lock Range 200 400 MHz
÷ 2 output 100 200
f
MAX Maximum Output Frequency ÷ 4 output 50 100 MH z
÷ 8 output 25 50
t
PD Propagation Delay (Static Phase Offset) TCLK to FBIN -50 150 ps
PECL_CLK to FBIN 25 325
tPLZ, tPHZ Output Disable Time 10 ns
tPZL, tPZH Output Enable Time 10 ns
÷ 2 feedback -3db point of 9 - 20
B
W PLL Closed Loop Bandwidth ÷ 4 feedback PLL transfer 3 - 9.5 MHz
÷ 8 feedback characteristic 1.2 - 2.1
t
J Cycle-to-Cycle Jitter ÷ 4 feedback RMS Value 10 22 ps
(Single Output Frequency Configuration)
tJIT ( PER) Period Jitter ÷ 4 feedback RMS Value 8 15 ps
(Single Output Frequency Configuration)
tJIT (φ) I/O Phase Jitter RMS Value 4 - 17 ps
tLOCK Maximum PLL Lock Time 1 ms
NOTES:
1. AC Characteristics apply for parallel output termination of 50Ω to VTT.
2. VCMR(AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range and the input swing lies within VPP(AC)
specifications.
INDUSTRIAL TEMPERATURE RANGE
6
IDT5V9351
LOW VOLTAGE PLL CLOCK DRIVER
DC ELECTRICAL CHARACTERISTICS
TA = -40°C to +85°C, VCC = 2.5V ± 5%
Symbol Parameter Test Conditions Min. Typ. Max Unit
VIH Input HIGH Voltage LVCMOS Inputs 1.7 VCC + 0.3 V
VIL Input LOW Voltage LVCMOS Inputs 0.7 V
VPP Peak-to-Peak Input Voltage PECL_CLK 250 mV
VCMR Common Mode
(1)
PECL_CLK 1 VCC - 0.6 V
VOH Output HIGH Voltage
(2)
IOH = -15mA 1.8 V
VOL Output LOW Voltage
(2)
IOL = 15mA 0.6 V
IIN Input Current ±150 μA
CIN Input Capacitance 4 pF
ZOUT Output Impedance 17 - 20 Ω
CPD Power Dissipation Capacitance 10 pF
ICC Maximum Quiescent Supply Current All VCC Pins 1 mA
I
CCPLL Maximum PLL Supply Current VCCA Only 3 5 mA
NOTES:
1. VCMR is the difference from the most positive side of the differential input signal. Normal operation is obtained when the HIGH input is within the VCMR range and the input swing
lies within the VPP specification.
2. The IDT5V9351 outputs can drive series or paralell terminated 50Ω (or 50Ω to VCC/2) transmission lines on the incident edge.
PLL INPUT REFERENCE CHARACTERISTICS
VCC = 2.5V ± 5%, TA = -40°C to +85°C
Symbol Parameter Min. Max Unit
tR, tF TCLK Input Rise/Fall Levels, 0.7V to 1.7V 1 ns
÷ 2 feedback 100 200
f
REF Reference Input Frequency
(1)
÷ 4 feedback 50 100 MHz
÷ 8 feedback 25 50
f
REFDC Reference Input Duty Cycle 25 75 %
NOTE:
1. Maximum and minimum input reference is limited by the VCO lock range and the feedback divider for the TCLK or PECL_CLK inputs.

IDT5V9351PFGI

Mfr. #:
Manufacturer:
Description:
IC CLOCK DRIVER PLL LV 32-TQFP
Lifecycle:
New from this manufacturer.
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