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ADM706TANZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
ADM706P/ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/ADM708T Data Sheet
Rev. E | Page 4 of 16
Parameter Min Typ Max Unit Test Conditions/Comments
WDO
OUTPUT VOLTAGE
V
OH
0.8 × V
CC
V V
RST
(max) < V
CC
< 3.6 V, I
SOURCE
= 500 μA
V
CC
− 1.5 V V 4.5 V < V
CC
< 5.5 V, I
SOURCE
= 800 μA
V
OL
0.3 V V
RST
(max) < V
CC
< 3.6 V, I
SINK
= 500 μA
0.4 V 4.5 V < V
CC
< 5.5 V, I
SINK
= 1.2 mA
MANUAL RESET INPUT
MR
Pull-Up Current (
MR
= 0 V) 25 70 250 μA V
RST
(max) < V
CC
< 3.6 V
100
250
600
4.5 V < V
CC
< 5.5 V
MR
Pulse Width 500 ns V
RST
(max) < V
CC
< 3.6 V
150 ns 4.5 V < V
CC
< 5.5 V
MR
INPUT THRESHOLD
V
IL
0.6 V V
RST
(max) < V
CC
< 3.6 V
V
IH
0.7 × V
CC
V V
RST
(max) < V
CC
< 3.6 V
V
IL
0.8 V 4.5 V < V
CC
< 5.5 V
V
IH
2.0 V 4.5 V < V
CC
< 5.5 V
MR
TO RESET OUTPUT DELAY 750 ns V
RST
(max) < V
CC
< 3.6 V
250 ns 4.5 V < V
CC
< 5.5 V
POWER FAIL INPUT
PFI Input Threshold 1.2 1.25 1.3 V ADM706P/ADM706R/ADM708R, V
CC
= 3 V
ADM706S/ADM708S/ADM706T/ADM708T,
V
CC
= 3.3 V, PFI falling
PFI Input Current
−25
+0.01
+25
PFO
OUTPUT VOLTAGE
V
OH
0.8 × V
CC
V V
RST
(max) < V
CC
< 3.6 V, I
SOURCE
= 500 μA
V
OL
0.3
V
RST
(max) < V
CC
< 3.6 V, I
SINK
= 1.2 mA
V
OH
V
CC
− 1.5 V V 4.5 V < V
CC
< 5.5 V, I
SOURCE
= 800 μA
V
OL
0.4 V 4.5 V < V
CC
< 5.5 V, I
SINK
= 3.2 mA
Data Sheet ADM706P/ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/ADM708T
Rev. E | Page 5 of 16
ABSOLUTE MAXIMUM RATINGS
T
A
= 25°C unless otherwise noted.
Table 2.
Parameter Rating
V
CC
−0.3 V to +6 V
All Other Inputs −0.3 V to V
CC
+ 0.3 V
Input Current
V
CC
20 mA
GND 20 mA
Digital Output Current 20 mA
Power Dissipation, N-8 (PDIP)
727 mW
θ
JA
Thermal Impedance 135°C/W
Power Dissipation, R-8 (SOIC) 470 mW
θ
JA
Thermal Impedance 110°C/W
Operating Temperature Range
Industrial (Version A) −40°C to +85°C
Lead Temperature (Soldering, 10 sec) 300°C
Vapor Phase (60 sec) 215°C
Infrared (15 sec) 220°C
Storage Temperature Range −65°C to +150°C
ESD Rating >4.5 kV
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
ADM706P/ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/ADM708T Data Sheet
Rev. E | Page 6 of 16
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
RESET
ADM706P
TOP VIEW
(Not to Scale)
1
2
3
4
5
8
7
6
06435-003
MR
PFO
WDI
WDO
V
CC
GND
PFI
Figure 3. ADM706P
RESET
T
OP
VIEW
(Not to Scale)
1
2
3
4
5
8
7
6
06435-004
MR
PFO
WDI
V
CC
GND
PFI
WDO
ADM706R/
ADM706S/
ADM706T
Figure 4. ADM706R/ADM706S/ADM706T
Table 3. Pin Function Descriptions ADM706P/ADM706R/ADM706S/ADM706T
Pin No. Mnemonic Description
1
MR
Manual Reset Input. When taken below 0.6 V, a RESET/
RESET
is generated.
MR
can be driven
from TTL, CMOS logic, or from a manual reset switch because it is internally debounced. An
internal 70 μA pull-up current holds the input high when floating.
2 V
CC
Power Supply Input. Place a 0.1 µF decoupling capacitor between the V
CC
and GND pins.
3 GND Ground. Ground reference for all signals (0 V).
4 PFI Power Fail Input. PFI is the noninverting input to the power fail comparator. When PFI is less
than 1.25 V,
PFO
goes low. If unused, PFI connects to GND.
5
PFO
Power Fail Output.
PFO
is the output from the power fail comparator. It goes low when PFI is
less than 1.25 V.
6 WDI Watchdog Input. If WDI remains either high or low for longer than the watchdog timeout period, the
watchdog output,
WDO
, goes low. The timer resets with each transition at the WDI input. Either
a high to low or a low to high transition clears the counter. The internal timer is also cleared
whenever reset is asserted.
7 (ADM706R/ADM706S/
ADM706T Only)
RESET
Logic Output.
RESET
goes low for 200 ms when triggered. It is triggered either by V
CC
being
below the reset threshold or by a low signal on the
MR
input.
RESET
remains low whenever V
CC
is below the reset threshold. It remains low for 200 ms after V
CC
goes above the reset threshold
or
MR
goes from low to high. A watchdog timeout does not trigger
RESET
unless
WDO
is
connected to
MR
.
7 (ADM706P Only)
RESET
Logic Output. RESET is an active high output suitable for systems that use active high reset logic. It is
the inverse of
RESET
.
8
WDO
Watchdog Output.
WDO
goes low if the internal watchdog timer times out as a result of inactivity on
the WDI input. It remains low until the watchdog timer is cleared.
WDO
also goes low during
low line conditions. Whenever V
CC
is below the reset threshold,
WDO
remains low. As soon as V
CC
goes above the reset threshold,
WDO
goes high immediately.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

ADM706TANZ

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Manufacturer:
Analog Devices Inc.
Description:
Supervisory Circuits RESET GENERATOR I.C.
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