EVAL-ADuM4120EBZ/EVAL-ADuM4120-1EBZ User Guide UG-1109
Rev. 0 | Page 3 of 5
SETTING UP THE EVAL-ADUM4120EBZ AND EVAL-ADUM4120-1EBZ
INITIAL CONFIGURATION
Be fore initial use, certain steps must be completed to prepare the
E VA L -ADuM4120EBZ or E VA L -ADuM4120-1EBZ evaluation
board for operation. In the stock configuration (see Figure 1),
the R1 to R4 resistors are not placed. These are the locations of
the series external resistors for the charging and discharging paths
of the device being driven. It is recommended to use 1206 surface-
mount resistors with values between approximately 1 Ω and 10 Ω,
depending on the load being driven. R1 and R2 provide parallel
placements, whereas R3 and R4 are in series. An actual insulated
gate bipolar transistor (IGBT) or metal-oxide semiconductor
field effect transistor (M OSFET) can be placed in the provided
Q1, Q2, or Q3 landing patterns. Jumper P1 allows shorting
across the series external resistors to observe overshoot and/or
allow the user to probe voltage to quantify peak currents.
Resistor R6 is provided if the user must terminate the V
IN
input
with a 50 Ω load. Placing a jumper in P4 connects the stock 50 Ω
load to the V
IN
pin. R6 is not required, and, if the P4 jumper is not
placed, the evaluation board accepts high impedance signal
generator signals.
Pins accompany the screw terminals. The user decides which
connection mechanism to use. The screw terminals aid in
connecting wires for longer term measurements, but are not
recommended for placement of the devices being driven. The
distance to the screw terminals for Jumpe r P6 is far from the gate
driver and introduces parasitic inductances to the measurement.
Jumper P3 allows the user to tie the V
IN
pin to VDD1 or GND1
quickly. If a jumper is installed in P3, do not attempt to drive the
V
IN
pin by an e xternal signal gene rator because this causes a short
condition. Only actively drive V
IN
when no jumper is placed in P3.
PAD LAYOUT FOR THE DEVICE UNDER TEST (DUT)
Figure 2 shows the top layer artwork for the dual-gate driver circuit.
Evaluation board components include the following:
• U1 is the footprint for the ADuM4120 or ADuM4120-1.
• C1 and C2 are 0.1 µF bypass capacitors; C3 is a 10 µF
bypass capacitor.
• Q1, Q2, and Q3 can be populated with TO-246, TO-252, or
TO-220 MOSFETs o r IGBTs (see Figure 2).
• R1 to R4 are gate resistors that control the edges of the
outputs. By default, no resistors are installed; these resistors
must be populated with low value 1206 resistors, generally
in the 1 Ω to 10 Ω range.
2
C/D
1
G
3
E/S
15606-002
Figure 2. IGBT/MOSFET Footprint
POWER CONNECTIONS
Follow these steps to connect the ADuM4120 or ADuM4120-1
evaluation board to a power supply:
1. Connect the input supply (2.5 V to 5.5 V) with the positive
terminal on VDD1 and the ground on GND1.
2. Connect the ADuM4120 or ADuM4120-1 VDD2 supply
voltage (4.5 V to 35 V) to the VDD2 pin and return to the
GND2 pin.
GND1 and GND2 are isolated from each other. The
emitter/source of the IGBT or MOSFET is tied to GND2.
INPUT/OUTPUT CONNECTIONS
The V
IN
pin is a complementary metal-oxide semiconductor
(CMOS) input. To drive the gate driver with positive logic,
connect the input signal to the V
IN
pin.
The E VA L -ADuM4120EBZ evaluation board has screw
terminals for both the input and output connections. These
terminals facilitate connection options but are not the best
option for high performance transient testing. The best
measurements performed on the load, whether it is an IGBT,
MOSFET, or load capacitor, come from small loop measurements
performed at the load. Using the screw terminals as either the
sensing node or for the connection of the load often results in
observing extra overshoot during measurement.
