NCP5500, NCV5500, NCP5501, NCV5501
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7
TYPICAL CHARACTERISTICS
Figure 15. Ripple Rejection vs. Frequency
f, FREQUENCY (kHz)
1001010.10.01
0
10
20
30
40
50
70
90
RR, RIPPLE REJECTION (dB)
60
80
V
in
= 6 V,
DV
in
= 0.5 V
pp
500 mA
100 mA
1 mA
V
out(nom)
= 1.5 V
Figure 16. Ripple Rejection vs. Frequency
f, FREQUENCY (kHz)
1001010.10.01
0
10
20
30
40
50
70
90
RR, RIPPLE REJECTION (dB)
60
80
500 mA
100 mA
1 mA
V
out(nom)
= 1.25 V (ADJ)
I
out
, OUTPUT CURRENT (mA)
500450250200150100500
0
1
3
4
5
7
9
10
ESR (W)
400350300
2
6
8
Unstable Region
Stable Region
Figure 17. Output Capacitor ESR Stability vs.
Output Current
I
out
, OUTPUT CURRENT (mA)
500450250200150100500
0
1
3
4
5
7
9
10
ESR (W)
400350300
2
6
8
Unstable Region
Stable Region
Figure 18. Output Capacitor ESR Stability vs.
Output Current
Figure 19. Output Capacitor ESR Stability vs.
Output Current
C
out
= 1 mF to 10 mF
V
out(nom)
= 5 V
Figure 20. Output Capacitor ESR Stability vs.
Output Current
C
out
= 1 mF to 10 mF
V
out(nom)
= 1.5 V
I
out
, OUTPUT CURRENT (mA)
ESR (W)
C
out
= 1 mF to 10 mF
V
out(nom)
= 3.3 V
C
out
= 1 mF to 10 mF
V
out(nom)
= 1.25 V (ADJ)
0
1
2
3
4
5
6
7
8
9
10
11
12
0 50 100 150 200 250 300 350 400 450 500500450250200150100500 400350300
0
1
2
3
4
5
6
7
8
9
10
0 50 100 150 200 250 300 350 400 450 500
I
out
, OUTPUT CURRENT (mA)
ESR (W)
Unstable Region
Stable Region
Unstable Region
Stable Region
V
in
= 6 V,
DV
in
= 0.5 V
pp
NOTE: Typical characteristics were measured with the same conditions as electrical characteristics, unless otherwise noted.
NCP5500, NCV5500, NCP5501, NCV5501
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8
Figure 21. Measuring Circuits
Input
Enable
Output
ADJ
GND
NCP5500
R
L
C
in
10 mF
C
in2
100 nF
EN
I
ADJ
I
GND
I
Q
I
EN
I
in
I
out
C
out
NCV5500
Input
Output
GND
R
L
C
in
10 mF
C
in2
100 nF
I
GND
I
Q
I
in
I
out
C
out
NCP5501 NCV5501
V
out
V
in
V
out
V
in
Circuit Description
The NCP5500/NCP5501/NCV5500/NCV5501 are
integrated linear regulators with a DC load current
capability of 500 mA. The output voltage is regulated by a
PNP pass transistor controlled by an error amplifier and
band gap reference. The choice of a PNP pass element
provides the lowest possible dropout voltage, particularly at
reduced load currents. Pass transistor base drive current is
controlled to prevent oversaturation. The regulator is
internally protected by both current limit and thermal
shutdown. Thermal shutdown occurs when the junction
temperature exceeds 150C. The NCV5500 includes an
enable/shutdown pin to turn off the regulator to a low current
drain standby state.
Regulator
The error amplifier compares the reference voltage to a
sample of the output voltage (V
out
) and drives the base of a
PNP series pass transistor via a buffer. The reference is a
bandgap design for enhanced temperature stability.
Saturation control of the PNP pass transistor is a function of
the load current and input voltage. Oversaturation of the
output power device is prevented, and quiescent current in
the ground pin is minimized.
Regulator Stability Considerations
The input capacitor is necessary to stabilize the input
impedance to reduce transient line influences. The output
capacitor helps determine three main characteristics of a
linear regulator: startup delay, load transient response and
loop stability. The capacitor value and type should be based
on cost, availability, size and temperature constraints. Refer
to Typical Operating Characteristics for stability regions.
Enable Input (NCP5500, NCV5500)
The enable pin is used to turn the regulator on or off. By
holding the pin at a voltage less than 0.4 V, the output of the
regulator will be turned off to a minimal current drain state.
When the voltage at the Enable pin is greater than 2.0 V, the
output of the regulator will be enabled and rise to the
regulated output voltage. The Enable pin may be connected
directly to the input pin to provide a constant enable to the
regulator.
Active Load Protection in Shutdown (NCP5500,
NCV5500)
When a linear regulator is disabled (shutdown), the output
(load) voltage should be zero. However, stray PC board
leakage paths, output capacitor dielectric absorption, and
inductively coupled power sources can cause an undesirable
regulator output voltage if load current is low or zero. The
NCV5500 features a load protection network that is active
only during Shutdown mode. This network switches in a
shunt current path (~500 mA) from V
out
to Ground. This
feature also provides a controlled (“soft”) discharge path for
the output capacitor after a transition from Enable to
Shutdown.
NCP5500, NCV5500, NCP5501, NCV5501
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9
Calculating Resistors for the ADJ Versions
The adjustable version uses feedback resistors to adjust
the output to the desired output voltage. With V
out
connected
to ADJ, the adjustable version will regulate at 1.25 V
4.9% (1250 61.25 mV).
Output voltage formula with an external resistor divider:
V
out
+
ǒ
1.25 V * ƪ60E9 @
(R
1
@ R
2)
(R
1
) R
2
)
ƫ
Ǔ
@
ǒ
(R
1
) R
2
)
R
2
Ǔ
Where
R
1
= value of the divider resistor connected between V
out
and ADJ,
R
2
= value of the divider resistor connected between ADJ
and GND,
The term “1.25 V” has a tolerance of 4.9%; the term
“60E9” can vary in the range 15E9 to 60E9.
For values of R
2
less than 15 KW, the term within brackets
( [ ] ) will evaluate to less than 1 mV and can be ignored. This
simplifies the output voltage formula to:
V
out
= 1.25 V * ((R1 + R2) / R2)) with a tolerance of 4.9%,
which is the tolerance of the 1.25 V output when delivering
up to 500 mA of output current.
DEFINITION OF TERMS
Dropout Voltage: The inputtooutput voltage differential
at which the circuit ceases to regulate against further
reduction input voltage. Measured when the output voltage
has dropped 2% relative to the value measured at nominal
input voltage. Dropout voltage is dependent upon load
current and junction temperature.
Input Voltage: The DC voltage applied to the input
terminals with respect to ground.
Line Regulation: The change in output voltage for a change
in the input voltage. The measurement is made under
conditions of low dissipation or by using pulse techniques
such that the average chip temperature is not significantly
affected.
Load Regulation: The change in output voltage for a change
in load current at constant chip temperature. Pulse loading
techniques are employed such that the average chip
temperature is not significantly affected.
Quiescent and Ground Current: The quiescent current is
the current which flows through the ground when the LDO
operates without a load on its output: internal IC operation,
bias, etc. When the LDO becomes loaded, this term is called
the Ground current. It is actually the difference between the
input current (measured through the LDO input pin) and the
output current.
Ripple Rejection: The ratio of the peaktopeak input ripple
voltage to the peaktopeak output ripple voltage.
Current Limit: Peak current that can be delivered to the
output.
Calculating Power Dissipation
The maximum power dissipation for a single output
regulator (Figure 21) is:
P
D(max)
+
ƪ
V
in(max)
* V
out(min)
ƫ
I
out(max)
) V
in(max)
I
GND
(eq. 1)
Where
V
in(max)
is the maximum input voltage,
V
out(min)
is the minimum output voltage,
I
out(max)
is the maximum output current for the application,
I
GND
is the ground current at I
out(max)
.
Once the value of P
D(max)
is known, the maximum
permissible value of R
q
JA
can be calculated:
R
qJA
+
ǒ
150 C * T
A
Ǔ
P
D
(eq. 2)
The value of R
q
JA
can then be compared with those in the
Thermal Characteristics table. Those packages with R
q
JA
less than the calculated value in Equation 2 will keep the die
temperature below 150C.
In some cases, none of the packages will be sufficient to
dissipate the heat generated by the IC, and an external heat
sink will be required.
Heat Sinks
A heat sink effectively increases the surface area of the
package to improve the flow of heat away from the IC and
into the surrounding air.
Each material in the heat flow path between the IC and the
outside environment will have a thermal resistance. Like
series electrical resistances, these resistances are summed to
determine the value of R
q
JA
:
R
qJA
+ R
qJC
) R
qCS
) R
qSA
(eq. 3)
where
R
q
JC
is the junctiontocase thermal resistance,
R
q
CS
is the casetoheatsink thermal resistance,
R
q
SA
is the heatsinktoambient thermal resistance.
R
q
JC
appears in the Thermal Characteristics table. Like
R
q
JA
, it too is a function of package type. R
q
CS
and R
q
SA
are
functions of the package type, heat sink and the interface
between them. These values appear in data sheets of heat
sink manufacturers.
Thermal, mounting, and heat sink considerations are
further discussed in ON Semiconductor Application Note
AN1040/D.

NCP5501DT33RKG

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
LDO Voltage Regulators 500 mA 3.3V LDO
Lifecycle:
New from this manufacturer.
Delivery:
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