LTC4215-1/LTC4215-3
11
421513fc
The LTC4215-1/LTC4215-3 are designed to turn a board’s
supply voltage on and off in a controlled manner, allowing
the board to be safely inserted or removed from a live
backplane. During normal operation, the charge pump
and gate driver turn on an external N-channel MOSFET’s
gate to pass power to the load. The gate driver uses a
charge pump that derives its power from the V
DD
pin.
Also included in the gate driver is an internal 6.5V GATE-
to-SOURCE clamp. During start-up the inrush current is
tightly controlled by using current limit foldback, soft start
dI/dt limiting and output dV/dt limiting.
The current sense (CS) amplifi er monitors the load current
using the difference between the SENSE
+
and SENSE
–
pin
voltages. The CS amplifi er limits the current in the load by
pulling back on the GATE-to-SOURCE voltage in an active
control loop when the sense voltage exceeds the com-
manded value. The CS amplifi er requires 20µA input bias
current from both the SENSE
+
and the SENSE
–
pins.
A short circuit on the output to ground results in excessive
power dissipation during active current limiting. To limit
this power, the CS amplifi er regulates the voltage between
the SENSE
+
and SENSE
–
pins at 75mV.
If an overcurrent condition persists, the internal circuit
breaker (CB) registers a fault when the sense voltage
exceeds 25mV for more than 20µs in the case of the
LTC4215-1 or 420µs in the case of the LTC4215-3. This
indicates to the logic that it is time to turn off the GATE
to prevent overheating. At this point the start-up TIMER
capacitor voltage ramps down using the 2µA current
source until the voltage drops below 0.2V (comparator
TM1) which tells the logic that the pass transistor has
cooled and it is safe to turn it on again if overcurrent
auto-retry is enabled. If the TIMER pin is tied to INTV
CC
,
the cool-down time defaults to 5 seconds on an internal
system timer in the logic.
The output voltage is monitored using the FB pin and the
Power Good (PG) comparator to determine if the power
is available for the load. The power good condition can be
signaled by the GPIO1 pin using an open-drain pull-down
transistor. The GPIO1 pin may also be confi gured to signal
power bad, or as a general purpose input (GP comparator),
or a general purpose open drain output.
GPIO2 and GPIO3 may also be confi gured as a general
purpose inputs or general purpose open drain outputs.
GPIO2 may also be confi gured to generate interrupts
when faults occur.
The Functional Diagram shows the monitoring blocks of
the LTC4215-1/LTC4215-3. The group of comparators on
the left side includes the undervoltage (UV), overvoltage
(OV), reset (RST), enable (EN) and (ON) comparators.
These comparators determine if the external conditions
are valid prior to turning on the GATE. But fi rst the two
undervoltage lockout circuits, UVLO1 and UVLO2, validate
the input supply and the internally generated 3.1V supply,
INTV
CC
. UVLO2 also generates the power-up initialization
to the logic circuits as INTV
CC
crosses this rising threshold.
If the fi xed internal overvoltage comparator, OV2, detects
that V
DD
is greater than 15.6V, the part immediately gener-
ates an overvoltage fault and turns the GATE off.
Included in the LTC4215-1/LTC4215-3 is an 8-bit A/D
converter. The converter has a 3-input multiplexer to
select between the ADIN pin, the SOURCE pin and the
V
DD
– SENSE voltage.
An I
2
C interface is provided to read the A/D registers. It
also allows the host to poll the device and determine if
faults have occurred. If the GPIO2 line is confi gured as an
ALERT interrupt, the host is enabled to respond to faults
in real time. The typical SDA line is divided into an SDAI
(input) and SDAO (output). This simplifi es applications
using an optoisolator driven directly from the SDAO out-
put. An application which uses optoisolation is shown in
the Typical Applications section. The I
2
C device address
is decoded using the ADR0 and ADR1 pins. These inputs
have three states each that decode into a total of 9 device
addresses.
OPERATION
