LTC4215-1/LTC4215-3
19
421513fc
Figure 6. Data Transfer Over I
2
C or SMBus
1.235V/R3 at the edge of the OV rising threshold, where
I
STRING
> 40µA. Then solve the following equations:
R2 =
V
OV(OFF)
V
UV(ON)
• R3
UV
TH(RISING)
OV
TH(FALLING)
– R3
R1 =
V
UV(ON)
•(R3+R2)
UV
TH(RISING)
–R3–R2
In our case we choose R3 to be 3.4k to give a resistor
string currrent below 10A. Then solving the equations
results in R2 = 1.16k and R1 = 34.6k.
The FB divider is solved by picking R8 and solving for R7,
choosing 3.57k for R8 we get:
R7 =
V
PWRGD(UP)
•R8
FB
TH(RISING)
–R8
Resulting in R7 = 30k.
A 0.1µF capacitor, C
F
, is placed on the UV pin to prevent
supply glitches from turning off the GATE via UV or OV.
The address is set with the help of Table 1, which indicates
binary address 1001011 corresponds to address 4. Address
4 is set by setting ADR1 open and ADR0 high.
Next the value of R5 and R6 are chosen to be the default
values 10Ω and 15k as discussed previously.
In addition a 0.1µF ceramic bypass capacitor is placed on
the INTV
CC
pin.
Layout Considerations
To achieve accurate current sensing, a Kelvin connection
is required. The minimum trace width for 1oz copper
foil is 0.02" per amp to make sure the trace stays at a
reasonable temperature. Using 0.03" per amp or wider
is recommended. Note that 1oz copper exhibits a sheet
resistance of about 530µΩ. Small resistances add up
quickly in high current applications. To improve noise
immunity, put the resistive dividers to the UV, OV and FB
pins close to the device and keep traces to V
DD
and GND
short. It is also important to put the bypass capacitor for
the INTV
CC
pin, C3, as close as possible between INTV
CC
and GND. A 0.1µF capacitor from the UV pin (and OV pin
through resistor R2) to GND also helps reject supply noise.
Figure 4 shows a layout that addresses these issues. Note
that a surge suppressor, Z1, is placed between supply and
ground using wide traces.
Digital Interface
The LTC4215-1/LTC4215-3 communicate with a bus mas-
ter using a 2-wire interface compatible with I
2
C Bus and
SMBus, an I
2
C extension for low power devices.
The LTC4215-1/LTC4215-3 are read-write slave devices
and support SMBus bus Read Byte, Write Byte, Read Word
and Write Word commands. The second word in a Read
Word command is identical to the fi rst word. The second
word in a Write Word command is ignored. Data formats
for these commands are shown in Figures 6 to 11.
START and STOP Conditions
When the bus is idle, both SCL and SDA are high. A bus
master signals the beginning of a transmission with a start
condition by transitioning SDA from high to low while SCL
is high, as shown in Figure 6. When the master has fi nished
communicating with the slave, it issues a STOP condition
by transitioning SDA from low to high while SCL is high.
The bus is then free for another transmission.
APPLICATIONS INFORMATION
SCL
SDA
START
CONDITION
STOP
CONDITION
ADDRESS R/W ACK DATA ACK DATA ACK
1 - 7 8 9
4215 F06
a6 - a0 b7 - b0 b7 - b0
1 - 7 8 9 1 - 7 8 9
P
S
LTC4215-1/LTC4215-3
20
421513fc
I
2
C Device Addressing
Nine distinct bus addresses are available using two 3-
state address pins, ADR0 and ADR1. Table 1 shows the
correspondence between pin states and addresses. Note
that address bits B7 and B6 are internally con gured to
“10”. In addition, the LTC4215-1/LTC4215-3 respond to
two special addresses. Address (1011 111) is a mass
write address that writes to all LTC4215-1/LTC4215-3s,
regardless of their individual address settings. Mass write
can be disabled by setting register bit A4 to zero. Address
(0001 100) is the SMBus Alert Response Address. If the
LTC4215-1/LTC4215-3 are pulling low on the GPIO2 pin due
to an alert, it acknowledges this address by broadcasting
its address and releasing the GPIO2 pin.
APPLICATIONS INFORMATION
Figure 7. LTC4215-1/LTC4215-3 Serial Bus SDA Write Byte Protocol
Figure 8. LTC4215-1/LTC4215-3 Serial Bus SDA Write Word Protocol
Figure 9. LTC4215-1/LTC4215-3 Serial Bus SDA Read Byte Protocol
Figure 10. LTC4215-1/LTC4215-3 Serial Bus SDA Read Word Protocol
Figure 11. LTC4215-1/LTC4215-3 Serial Bus SDA Alert Response Protocol
S ADDRESS
1 0 a4:a0
4215 F07
FROM MASTER TO SLAVE
FROM SLAVE TO MASTER
A: ACKNOWLEDGE (LOW)
A: NOT ACKNOWLEDGE (HIGH)
R: READ BIT (HIGH)
W: WRITE BIT (LOW)
S: START CONDITION
P: STOP CONDITION
COMMAND DATA
X X X X X b2:b00
W
000b7:b0
A A AP
S ADDRESS
1 0 a4:a0
COMMAND DATA DATA
X X X X X b2:b00
W
000 0
4215 F08
X X X X X X X Xb7:b0
A
A A AP
S ADDRESS
1 0 a4:a0 1 0 a4:a0 1 0
COMMAND S ADDRESS R A
b7:b0 1
DATA
X X X X X b2:b00
W
00
4215 F10
A A A P
S ADDRESS
1 0 a4:a0 1 0 a4:a0 1 0
COMMAND S ADDRESS R A
b7:b0 1
DATA
X X X X X b2:b00
W
00
4215 F11
A
0
A
b7:b0
DATA
A A P
S
ALERT
RESPONSE
ADDRESS
0 0 0 1 1 0 0
DEVICE
ADDRESS
1 0 a4:a0 0 11
R
0
4215 F11
A A
P
LTC4215-1/LTC4215-3
21
421513fc
Figure 12. Control Logic for GPIO2 Pin
4215 TA02
RISING
EDGE
DETECT
IQ
RISING
EDGE
DETECT
IQ
• • •
STATUS BIT C0
ALERT ENABLE BIT B0
POWER ON RESET
I
2
C ADDRESS ACK
STATUS BIT C5
ALERT ENABLE BIT B5
REGISTER BIT D6
GPIO2 PIN
S
R
Q
APPLICATIONS INFORMATION
Acknowledge
The acknowledge signal is used in handshaking between
transmitter and receiver to indicate that the last byte of
data was received. The transmitter always releases the
SDA line during the acknowledge clock pulse. When the
slave is the receiver, it pulls down the SDA line so that it
remains LOW during this pulse to acknowledge receipt
of the data. If the slave fails to acknowledge by leaving
SDA high, then the master may abort the transmission by
generating a STOP condition. When the master is receiv-
ing data from the slave, the master pulls down the SDA
line during the clock pulse to indicate receipt of the data.
After the last byte has been received the master leaves
the SDA line HIGH (not acknowledge) and issues a stop
condition to terminate the transmission.
Write Protocol
The master begins communication with a START con-
dition followed by the seven bit slave address and the
R/W bit set to zero, as shown in Figure 7. The addressed
LTC4215-1/LTC4215-3 acknowledge this and then the
master sends a command byte which indicates which
internal register the master wishes to write. The LTC4215-
1/LTC4215-3 acknowledge this and then latch the lower
three bits of the command byte into its internal Register
Address pointer. The master then delivers the data byte
and the LTC4215-1/LTC4215-3 acknowledge once more
and latch the data into its control register. The transmis-
sion is ended when the master sends a STOP condition.
If the master continues sending a second data byte, as
in a Write Word command, the second data byte is ac-
knowledged by the LTC4215-1/LTC4215-3 but ignored,
as shown in Figure 8.
Read Protocol
The master begins a read operation with a START condition
followed by the seven bit slave address and the R/W bit set
to zero, as shown in Figure 9. The addressed LTC4215-1/
LTC4215-3 acknowledge this and then the master sends
a command byte which indicates which internal register
the master wishes to read. The LTC4215-1/LTC4215-3
acknowledge this and then latch the lower three bits of the
command byte into its internal Register Address pointer.
The master then sends a repeated START condition followed
by the same seven bit address with the R/W bit now set
to one. The LTC4215-1/LTC4215-3 acknowledge and send
the contents of the requested register. The transmission
is ended when the master sends a STOP condition. If the

LTC4215IUFD-1#TRPBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Hot Swap Voltage Controllers Hot Swap Contr. w/ADC and I2C
Lifecycle:
New from this manufacturer.
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