LTC6400-14
13
640014fb
which is dominated by a low pass fi lter connected to the
V
OCM
pin and is aimed to reduce common mode noise
generation at the outputs. The internal common mode
feedback loop has a –3dB bandwidth around 400MHz,
allowing fast common mode rejection at the outputs of
the LTC6400-14. The V
OCM
pin should be tied to a DC bias
voltage with a 0.1μF bypass capacitor. When interfacing
with A/D converters such as the LTC22xx families, the V
OCM
pin can be connected to the V
CM
pin of the ADC.
Driving A/D Converters
The LTC6400-14 has been specifi cally designed to inter-
face directly with high speed A/D converters. In Figure 7,
an example schematic shows the LTC6400-14 with a
single-ended input driving the LTC2208, which is a 16-bit,
130Msps ADC. Two external 4.99Ω resistors help eliminate
potential resonance associated with stray capacitance of
PCB traces and bond wires of either the ADC input or the
driver output. V
OCM
of the LTC6400-14 is connected to V
CM
of the LTC2208 V
CM
pin at 1.25V. Alternatively, a single-
ended input signal can be converted to a differential signal
via a balun and fed to the input of the LTC6400-14.
Figure 8 summarizes the IMD3 of the whole system in
Figure 7. Note that Figure 7 shows a direct connection
to the LTC2208, but in many applications an anti-alias
lter would be desirable to limit the wideband noise of
the amplifi er. This is especially true in high performance
16-bit designs.
Test Circuits
Due to the fully-differential design of the LTC6400 and
its usefulness in applications with differing characteristic
Figure 7. Single-Ended Input to LTC6400-14 and LTC2208
Figure 8. IMD3 for the Combination of LTC6400-14 and LTC2208
APPLICATIONS INFORMATION
29Ω
66.5Ω
0.1μF
0.1μF
640014 F07
LTC6400-14
V
OCM
ENABLE
IF IN
LTC2208
4.99Ω
0.1μF
LTC2208 130Msps
16-Bit ADC
1.25V
4.99Ω
14dB GAIN
AIN
AIN
+
V
CM
–IN
+IN
+OUT
+OUTF
–OUTF
–OUT
FREQUENCY (MHz)
0
IMD3 (dBc)
–40
–110
–100
–90
–80
–70
–60
–50
100 15050 200
640014 F08
250 300
SINGLE-ENDED INPUT
f
S
= 122.8Msps
DRIVER V
OUT
= 2V
P-P
COMPOSITE
Top Silkscreen
specifi cations, two test circuits are used to generate the
information in this datasheet. Test Circuit A is DC987B,
a two-port demonstration circuit for the LTC6400 family.
The schematic and silkscreen are shown below. This
circuit includes input and output transformers (baluns)
for single-ended-to-differential conversion and impedance
transformation, allowing direct hook-up to a 2-port
LTC6400-14
14
640014fb
TYPICAL APPLICATIONS
Demo Circuit 987B Schematic (Test Circuit A)
T1
(2)
T3
TCM 4-19
1:4
VERSION IC R3 R4 T1 SL1 SL2 SL3
T4
TCM 4-19
1:4
T2
TCM 4-19
-B LTC6400CUD-14 OPEN OPEN MINI-CIRCUITS TCM4-19 (1:4) 6dB 14dB 8dB
640014 TA03
R10
86.6Ω
R8
(1)
R7
(1)
R9
86.6Ω
C3
0.1μF
C4
0.1μF
C1
0.1μF
C2
0.1μF
LTC6400-14
V
OCM
V
+
V
+
V
V
V
+
V
CC
V
CC
V
ENABLE
+IN
+IN
–IN
–IN –OUT
+OUTF
–OUTF
+OUT
ENABLE DIS
12 11 10 9
1234
5
6
7
8
16
15
14
13
SL1
(2)
SL2
(2)
J2
–IN
J1
+IN
J5
–OUT
SL3
(2)
J4
+OUT
C22
0.1μF
C21
0.1μF
C18
0.1μF
C13
0.1μF
C17
1000pF
R16
TP2
V
CC
2.85V TO 3.5V
13
2
JP1
V
CC
V
CC
V
CC
C12
1000pF
C9
1000pF
C10
0.1μF
C15
1μF
V
CC
C14
4.7μF
C7
0.1μF
R4
(2)
1
3
2
3
1
2
5
4
4
5
TP5
V
OCM
R2
(1)
R1
R3
(2)
J6
TEST IN
C19
0.1μF
1
3
2
5
4
C20
0.1μF
R21
(1)
R22
(1)
R20
1k
R19
1.5k
R14
(1)
R13
C6
0.1μF
C5
0.1μF
C24
0.1μF
C23
0.1μF
J7
TEST OUT
NOTE: UNLESS OTHERWISE SPECIFIED.
(1) DO NOT STUFF.
(2)
SL = SIGNAL LEVEL
SL LEVELS DO NOT INCLUDE TRANSFORMER LOSS IN T1 AND T2
3
1
2
4
5
TP3
GND
R17
R25
R18
R26
R12
R11
(1)
R24
(1)
R6
R5
(1)
0dB
network analyzer. There are also series resistors at the
output to present the LTC6400 with a 375Ω differential
load, optimizing distortion performance. Due to the input
and output transformers, the –3dB bandwidth is reduced
from 2.4GHz to approximately 1.8GHz.
Test Circuit B uses a 4-port network analyzer to measure
S-parameters and gain/phase response. This removes the
effects of the wideband baluns and associated circuitry,
for a true picture of the >1GHz S-parameters and AC
characteristics.
APPLICATIONS INFORMATION
LTC6400-14
15
640014fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
PACKAGE DESCRIPTION
3.00 ± 0.10
(4 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
1.45 ± 0.05
(4 SIDES)
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WEED-2)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
PIN 1
TOP MARK
(NOTE 6)
0.40 ± 0.10
BOTTOM VIEW—EXPOSED PAD
1.45 ± 0.10
(4-SIDES)
0.75 ± 0.05
R = 0.115
TYP
0.25 ± 0.05
1
PIN 1 NOTCH R = 0.20 TYP
OR 0.25 × 45° CHAMFER
15 16
2
0.50 BSC
0.200 REF
2.10 ± 0.05
3.50 ± 0.05
0.70 ±0.05
0.00 – 0.05
(UD16) QFN 0904
0.25 ±0.05
0.50 BSC
PACKAGE
OUTLINE
UD Package
16-Lead Plastic QFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1691)
TYPICAL APPLICATIONS
Test Circuit B, 4-Port Analysis
0.1μF
13
640014 TA02
1
V
+
2
V
OCM
14
7
15
+OUT
+OUTF
–OUTF
–OUT
+IN
IN+ OUT–
IN– OUT+
+IN
–IN
–IN
516
R
G
100Ω
R
OUT
12.5Ω
R
F
500Ω
R
G
100Ω
R
F
500Ω
6
4
V
3
V
+
V
OCM
V
+
V
+
12
V
11
ENABLE
9
V
10
V
+
COMMON
MODE CONTROL
1/2
AGILENT
E5O71A
BIAS CONTROL
8
R
OUT
12.5Ω
37.4Ω
37.4Ω
R
FILT
50Ω
R
FILT
50Ω
C
FILT
2.7pF
1000pF
0.1μF
0.1μF
0.1μF
PORT 3
(50Ω)
PORT 4
(50Ω)
1/2
AGILENT
E5O71A
200Ω
0.1μF
0.1μF
PORT 1
(50Ω)
PORT 2
(50Ω)
0.1μF
1000pF
LTC6400-14

LTC6400CUD-14#TRPBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
High Speed Operational Amplifiers 3GHz Low Noise/Low Distortion Differential Amp
Lifecycle:
New from this manufacturer.
Delivery:
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