BD3573HFP-TR

Technical Note
4/9
BD3570FP/HFP, BD3571FP/HFP, BD3572FP/HFP, BD3573FP/HFP
BD3574FP/HFP, BD3575FP/HFP
www.rohm.com
2011.03 - Rev.B
© 2011 ROHM Co., Ltd. All rights reserved.
Block Diagram
I/O Circuit diagram (All resistance values are typical.)
Pin Assignments
TO252-3
TO252-5
HRP5
Pin No. Pin name Function
1 VCC Power supply pin
2 N.C. N.C. pin
3 VO Voltage output pin
Fin GND GND pin
Pin No. Pin name Function
1 VCC Power supply pin
2
SW
N.C.
V
O ON/OFF function pin
N.C. pin(BD3572FP only)
3 N.C. N.C. pin
4
N.C.
ADJ
N.C. pin
Output voltage setting pin(BD3572,3575FP only)
5 VO Voltage output pin
Fin GND GND pin
Pin No. Pin name Function
1 VCC Power supply pin
2
SW
N.C.
V
O ON/OFF function pin (BD3573,3574,3575HFP only)
N.C. pin
3 GND GND pin
4
N.C.
ADJ
N.C. pin
Output voltage setting pin(BD3572,3575HFP only)
5 VO Voltage output pin
Fin GND GND pin
1 23
FIN
Fig. 19
FIN
1
234 5
Fig.20
Fig. 21
12 3 45
FIN
GND
Vcc
Vref
OCP
TSD
Vo
Fin
1
N.C.
2
3
Cin
Fig.13 TO252-3
Cin0.33μF1000μF
Co0.1μF1000μF
Co
Fig.14 TO252-5
Vo
Co
ADJ (N.C.
1)
)
GND
Vcc
Vref
OCP
TSD
Fin
1
5
Cin
4
1
2
2
SW
GND
Vref
OCP
TSD
Vo
5
Co
4
Fin
SW
2
3
N.C.
ADJ (N.C.
1)
)
1
2
1For Fixed Voltage Regulator only
2For adjustable Voltage Regulator only
Fig.15 HRP5
Vcc
1
Cin
3
Fig.16 2PIN[SW]
SW
210K
1K
200K
Fig.17 5PIN[VO]
BD3570,3571,3573,3574
Vcc
Vo
1992K: BD3570, BD3573
3706K: BD3571, BD3574
1250K
Fig.18 4.5PIN[ADJ,VO]
BD3572,BD3575
Vcc
Vo
150
Technical Note
5/9
BD3570FP/HFP, BD3571FP/HFP, BD3572FP/HFP, BD3573FP/HFP
BD3574FP/HFP, BD3575FP/HFP
www.rohm.com
2011.03 - Rev.B
© 2011 ROHM Co., Ltd. All rights reserved.
Output Voltage Adjustment
To set the output voltage insert pull-down resistor R1 between the ADJ and GND pins,
and pull-up resistor R2 between the VO and ADJ pins.
Vo = VADJ×(R1+R2) / R1 [V]
VADJ=1.26V(TYP.)
The recommended connection resistor for the ADJ-GND is 30k150kΩ.
Setting of Heat
TO252-3 TO252-5 HRP5
Fig. 23 Fig. 24 Fig. 25
Refer to the heat mitigation characteristics illustrated in Figs. 23, 24 and 25 when using the IC in an environment where Ta
25. The characteristics of the IC are greatly influenced by the operating temperature. If the temperature is in excess of
the maximum junction temperature T
jmax, the elements of the IC may be deteriorated or damaged. It is necessary to give
sufficient consideration to the heat of the IC in view of two points, i.e., the protection of the IC from instantaneous damage
and the maintenance of the reliability of the IC in long-time operation.
In order to protect the IC from thermal destruction, it is necessary to operate the IC not in excess of the maximum junction
temperature T
jmax. Fig. 23 illustrates the power dissipation/heat mitigation characteristics for the TO252 package. Operate
the IC within the power dissipation Pd. The following method is used to calculate the power consumption P
C (W).
Vcc : Input voltage
PC=(VCC-VO)×IO+VCC×ICC Vo : Output voltage
Power dissipation PdPC Io : Load current
Icc : Total supply current
The load current I
O is obtained to operate the IC within the power dissipation.
(For more information about ICC, see page 12.)
The maximum load current Iomax for the applied voltage VCC can be calculated during the thermal design process.
Calculation example
Example: BD3571FP V
CC = 12 V and VO = 5 V at Ta = 85
I
O89mA (ICC=30μA)
Make a thermal calculation in consideration of the above so that the whole operating temperature range will be within the
power dissipation.
The power consumption Pc of the IC in the event of shorting (i.e., if the V
O and GND pins are shorted) will be obtained from
the following equation.
Pc=VCC×(ICC+Ishort) Ishort = Short current
V
CC-VO
Io
Pd-V
CC×ICC
IO
0.624-12×ICC
12-5
θja=104.2/W-9.6mAW/
25=1.2W85=0.624W
0
0.4
1.2 W
0
0.8
1.2
1.6
2.0
25 50 75 100 125 150
IC mounted on a ROHM standard board
Substrate size: 70 mm 70 mm 1.6 mm
ja = 104.2 (°C/W)
A
MBIENT TEMPERATURE: Ta [°C]
POWER DISSIPATION: Pd [W]
0
0.4
1.6 W
0
0.8
1.2
1.6
2.0
25 50 75 100 125 150
IC mounted on a ROHM standard board
Substrate size: 70 mm 70 mm 1.6 mm
ja = 78.1 (°C/W)
A
MBIENT TEMPERATURE: Ta [°C]
POWER DISSIPATION: Pd [W]
0
0.4
1.3W
0
0.8
1.2
1.6
2.0
25 50 75 100 125 150
A
MBIENT TEMPERATURE: Ta []
POWER DISSIPATION: Pd [W]
IC mounted on a ROHM standard board
Substrate size: 70 mm 70 mm 1.6 mm
ja = 96.2 (°C/W)
Fig.22
ADJ
Vo
R2
R1
Technical Note
6/9
BD3570FP/HFP, BD3571FP/HFP, BD3572FP/HFP, BD3573FP/HFP
BD3574FP/HFP, BD3575FP/HFP
www.rohm.com
2011.03 - Rev.B
© 2011 ROHM Co., Ltd. All rights reserved.
Peripheral Settings for Pins and Precautions
1) V
CC pins
Insert capacitors with a capacitance of 0.33μF to 1000μF between the V
CC and GND pins.
The capacitance varies with the application. Be sure to design the capacitance with a sufficient margin.
2) Capacitors for stopping oscillation for output pins
Capacitors for stopping oscillation must be placed between each output pin and the GND pin. Use a capacitor within a
capacitance range between 0.1μF and 1000μF. Since oscillation does not occur even for ESR values from 0.001Ω to
100Ω, a ceramic capacitor can be used. Abrupt input voltage and load fluctuations can affect output voltages. Output
capacitor capacitance values should be determined after sufficient testing of the actual application.
Operation Notes
1) Absolute maximum ratings
Use of the IC in excess of absolute maximum ratings such as the applied voltage or operating temperature range may
result in IC damage. Assumptions should not be made regarding the state of the IC (short mode or open mode) when
such damage is suffered. A physical safety measure such as a fuse should be implemented when use of the IC in a
special mode where the absolute maximum ratings may be exceeded is anticipated.
2) GND potential
Ensure a minimum GND pin potential in all operating conditions.
3) Setting of heat
Use a thermal design that allows for a sufficient margin in light of the power dissipation (Pd) in actual operating conditions.
4) Pin short and mistake fitting
Use caution when orienting and positioning the IC for mounting on printed circuit boards. Improper mounting may result in
damage to the IC. Shorts between output pins or between output pins and the power supply and GND pins caused by the
presence of a foreign object may result in damage to the IC.
5) Actions in strong magnetic field
Use caution when using the IC in the presence of a strong magnetic field as doing so may cause the IC to malfunction.
6) Testing on application boards
When testing the IC on an application board, connecting a capacitor to a pin with low impedance subjects the IC to stress.
Always discharge capacitors after each process or step. Be sure to turn power off when mounting or dismounting jigs at
the inspection stage. Furthermore, for countermeasures against static electricity, ground the equipment at the assembling
stage and pay utmost attention at the time of transportation or storing the product.
7) This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them isolated.
PN junction is formed by the P layer and the N layer of each element, and a variety of parasitic elements will be
constituted.
For example, when a resistor and transistor are connected to pins as shown in Fig. 19,
the P/N junction functions as a parasitic diode when GND>Pin A for the resistor or GND>Pin B for the transistor
(NPN).
Similarly, when GNDPin B for the transistor (NPN), the parasitic diode described above combines with the N
layer of other adjacent elements to operate as a parasitic NPN transistor.

BD3573HFP-TR

Mfr. #:
Manufacturer:
Description:
LDO Voltage Regulators LDO REGULATOR POS 3.3V 0.5A 6PIN
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