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ispLSI 1048E-90LQN

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
ispLSI
®
1048E
In-System Programmable High Density PLD
1048e_12 1
USE ispLSI 1048EA FOR NEW DESIGNS
Lead-
Free
Package
Options
Available!
Functional Block DiagramFeatures
• HIGH DENSITY PROGRAMMABLE LOGIC
— 8,000 PLD Gates
— 96 I/O Pins, Twelve Dedicated Inputs
— 288 Registers
— High-Speed Global Interconnects
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
— Functionally and Pin-out Compatible to ispLSI 1048C
• HIGH PERFORMANCE E
2
CMOS
®
TECHNOLOGY
—
fmax = 125 MHz Maximum Operating Frequency
—
tpd = 7.5 ns Propagation Delay
— TTL Compatible Inputs and Outputs
— Electrically Eraseable and Reprogrammable
— Non-Volatile
— 100% Tested at Time of Manufacture
• IN-SYSTEM PROGRAMMABLE
— In-System Programmable (ISP™) 5V Only
— Increased Manufacturing Yields, Reduced Time-to-
Market and Improved Product Quality
— Reprogram Soldered Devices for Faster Prototyping
• OFFERS THE EASE OF USE AND FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS
— Complete Programmable Device Can Combine Glue
Logic and Structured Designs
— Enhanced Pin Locking Capability
— Four Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control to
Minimize Switching Noise
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
— Lead-Free Package Options
Output Routing Pool
Output Routing Pool
F7 F6 F5 F4 F3 F2 F1 F0
B0 B1 B2 B3 B4 B5 B6 B7
A0
A1
A2
A3
A4
A5
A6
A7
Output Routing Pool
Output Routing Pool
Output Routing Pool
CLK
E7 E6 E5 E4 E3 E2 E1 E0
C0 C1 C2 C3 C4 C5 C6 C7
D7
D6
D5
D4
D3
D2
D1
D0
Output Routing Pool
Logic
Array
DQ
DQ
DQ
DQ
Global Routing Pool (GRP) GLB
0139G1A-isp
Description
The ispLSI 1048E is a High Density Programmable Logic
Device containing 288 Registers, 96 Universal I/O pins,
12 Dedicated Input pins, four Dedicated Clock Input pins,
two dedicated Global OE input pins, and a Global Routing
Pool (GRP). The GRP provides complete interconnectivity
between all of these elements. The ispLSI 1048E offers
5V non-volatile in-system programmability of the logic, as
well as the interconnect to provide truly reconfigurable
systems. A functional superset of the ispLSI 1048 archi-
tecture, the ispLSI 1048E device adds two new global
output enable pins and two additional dedicated inputs.
The basic unit of logic on the ispLSI 1048E device is the
Generic Logic Block (GLB). The GLBs are labeled A0,
A1…F7 (see Figure 1). There are a total of 48 GLBs in the
ispLSI 1048E device. Each GLB has 18 inputs, a pro-
grammable AND/OR/Exclusive OR array, and four outputs
which can be configured to be either combinatorial or
registered. Inputs to the GLB come from the GRP and
dedicated inputs. All of the GLB outputs are brought back
into the GRP so that they can be connected to the inputs
of any other GLB on the device.
Copyright © 2006 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. August 2006
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
Specifications ispLSI 1048E
2
USE ispLSI 1048EA FOR NEW DESIGNS
Functional Block Diagram
Figure 1. ispLSI 1048E Functional Block Diagram
The device also has 96 I/O cells, each of which is directly
connected to an I/O pin. Each I/O cell can be individually
programmed to be a combinatorial input, registered in-
put, latched input, output or bi-directional
I/O pin with 3-state control. The signal levels are TTL
compatible voltages and the output drivers can source 4
mA or sink 8 mA. Each output can be programmed
independently for fast or slow output slew rate to mini-
mize overall output switching noise.
Eight GLBs, 16 I/O cells, two dedicated inputs and one
ORP are connected together to make a Megablock (see
figure 1). The outputs of the eight GLBs are connected to
a set of 16 universal I/O cells by the ORP. Each ispLSI
1048E device contains six Megablocks.
The GRP has, as its inputs, the outputs from all of the
GLBs and all of the inputs from the bi-directional I/O cells.
All of these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.
Clocks in the ispLSI 1048E device are selected using the
Clock Distribution Network. Four dedicated clock pins
(Y0, Y1, Y2 and Y3) are brought into the distribution
network, and five clock outputs (CLK 0, CLK 1, CLK 2,
IOCLK 0 and IOCLK 1) are provided to route clocks to the
GLBs and I/O cells. The Clock Distribution Network can
also be driven from a special clock GLB (D0). The logic
of this GLB allows the user to create an internal clock
from a combination of internal signals within the device.
Output Routing Pool (ORP)
B0 B1 B2 B3 B4 B5 B6 B7
Output Routing Pool (ORP)
C0 C1 C2 C3 C4 C5 C6 C7
Output Routing Pool (ORP)
F7 F6 F5 F4 F3 F2 F1 F0
Input Bus
Output Routing Pool (ORP)
E7 E6 E5 E4 E3 E2 E1 E0
Input Bus
A0
A1
A2
A3
A4
A5
A6
A7
Output Routing Pool (ORP)
Generic
Logic Blocks
(GLBs)
Megablock
Input Bus
Global
Routing
Pool
(GRP)
CLK 0
CLK 1
CLK 2
IOCLK 0
IOCLK 1
Clock
Distribution
Network
D7
D6
D5
D4
D3
D2
D1
D0
Output Routing Pool (ORP)
I/O
94
I/O
95
I/O
93
I/O
92
I/O
91
I/O
90
I/O
89
I/O
88
I/O
87
I/O
86
I/O
85
I/O
84
I/O
83
I/O
82
I/O
81
I/O
80
IN
11
I/O
78
I/O
79
I/O
77
I/O
76
I/O
75
I/O
74
I/O
73
I/O
72
I/O
71
I/O
70
I/O
69
I/O
68
I/O
67
I/O
66
I/O
65
I/O
64
IN
9
IN
10
I/O
17
I/O
16
I/O
18
I/O
19
I/O
20
I/O
21
I/O
22
I/O
23
I/O
24
I/O
25
I/O
26
I/O
27
I/O
28
I/O
29
I/O
30
I/O
31
SDO/
IN 3
Y
0
Y
1
Y
2
Y
3
I/O
33
I/O
32
I/O
34
I/O
35
I/O
36
I/O
37
I/O
38
I/O
39
I/O
40
I/O
41
I/O
42
I/O
43
I/O
44
I/O
45
I/O
46
I/O
47
SCLK/
IN 5
IN
4
IN 7
IN 6
I/O 63
I/O 62
I/O 61
I/O 60
I/O 59
I/O 58
I/O 57
I/O 56
I/O 55
I/O 54
I/O 53
I/O 52
I/O 51
I/O 50
I/O 49
I/O 48
I/O 0
I/O 1
I/O 2
I/O 3
I/O 6
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
SDI/IN 0
MODE/IN 1
I/O 4
I/O 5
ispEN
RESET
Input Bus
Input Bus
lnput Bus
0139F(2)-48B-isp
IN
8
GOE 0
GOE 1
IN 2
Specifications ispLSI 1048E
3
USE ispLSI 1048EA FOR NEW DESIGNS
Absolute Maximum Ratings
1
Supply Voltage V
cc
. ................................. -0.5 to +7.0V
Input Voltage Applied........................ -2.5 to V
CC
+1.0V
Off-State Output Voltage Applied ..... -2.5 to V
CC
+1.0V
Storage Temperature ................................ -65 to 150°C
Case Temp. with Power Applied .............. -55 to 125°C
Max. Junction Temp. (T
J
) with Power Applied ... 150°C
1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).
DC Recommended Operating Conditions
Capacitance (T
A
=25
o
C, f=1.0 MHz)
Data Retention Specifications
C
SYMBOL
Table 2-0006/1048E
C
PARAMETER
Y0 Clock Capacitance
15
UNITSTYPICAL TEST CONDITIONS
1
2
8
Dedicated Input, I/O, Y1, Y2, Y3, Clock Capacitance
pf
pf
V = 5.0V, V = 2.0V
V = 5.0V, V = 2.0V
CC
CC PIN
PIN
T
A
= 0°C to + 70°C
T
A
= -40°C to + 85°C
SYMBOL
Table 2-0005/1048E
V
CC
V
IH
V
IL
PARAMETER
Supply Voltage
Input High Voltage
Input Low Voltage
MIN. MAX. UNITS
4.75
4.5
2.0
0
5.25
5.5
V
cc
+1
0.8
V
V
V
V
Commercial
Industrial
Table 2-0008/1048E
PARAMETER
Data Retention
MINIMUM MAXIMUM UNITS
Erase/Reprogram Cycles
20
10000
–
–
Years
Cycles
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

ispLSI 1048E-90LQN

Mfr. #:
Buy ispLSI 1048E-90LQN
Manufacturer:
Lattice
Description:
CPLD - Complex Programmable Logic Devices USE ispMACH 4000V
Lifecycle:
New from this manufacturer.
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