TCP-5056UB-DT Datasheet TCP-5056UB-DT | P4-P6

TCP−5056UB

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Representative performance data at 255C for 5.6 pF WLCSP Package

Figure 2. Capacitance

Figure 3. Harmonic Power*

Figure 4. IP3* Figure 5. Q*

*Data shown is representative only.

Table 3. ABSOLUTE MAXIMUM RATINGS

Parameter Rating Units

Input Power +40 dBm

Bias Voltage +30 (Note 6) V

Operating Temperature Range −30 to +85 °C

Storage Temperature Range −55 to +125 °C

ESD − Human Body Model Class 1B JEDEC HBM Standard (Note 7)

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

6. WLCSP: Recommended Bias Voltage not to exceed 24 V.

7. Class 1B defined as passing 500 V, but may fail after exposure to 1000 V ESD pulse.

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ASSEMBLY CONSIDERATIONS AND REFLOW PROFILE

The following assembly considerations should be observed:

Cleanliness

These chips should be handled in a clean environment.

Electro−static Sensitivity

ON Semiconductor’s PTICs are ESD Class 1B sensitive.

The proper ESD handling procedures should be used.

Mounting

The WLCSP PTIC is fabricated for Flip Chip solder

mounting. Connectivity to the RF and Bias terminations on

the PTIC die is established through SAC305 solder balls

with 90 mm nominal height (65 mm to 115 mm height

variation). The PTIC die is RoHS−compliant and

compatible with lead−free soldering profile.

Molding

The PTIC die is compatible for over−molding or

under−fill.

Figure 6. Reflow Profile

ORIENTATION OF THE PTIC FOR OPTIMUM LOSSES

When configuring the PTIC in your specific circuit

design, at least one of the RF terminals must be connected

to DC ground. If minimum transition times are required, DC

ground on both RF terminals is recommended. To minimize

losses, the PTIC should be oriented such that RF2

is at the

lower RF impedance of the two RF nodes. A shunt PTIC, for

example, should have RF2

connected to RF ground.

Figure 7. PTIC Orientation Functional Block

Diagram

Bias

RF ANT

RF1

(PTIC Pad)

RF2

(PTIC Pad)

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PART NUMBER DEFINITION

Table 4. PART NUMBERS

Part Number

Capacitance Marking

Package*

2 V 24 V Device ID Trace Code

TCP−5056UB−DT 5.6 1.204 G YW** 6−bump WLCSP

*See PTIC package dimensions on following page.

**Refer to table below (Table 5) for YW trace code.

For information on device numbering and ordering codes, please download the Device Nomenclature technical note

(TND310/D) from www.onsemi.com

Table 5. Two Digits Year and Work Week Date coding (YW) − In Process Product / Traceability Date Code Marking

Code

Term Definition

YW Year and

Work Week

Two−character Alpha Code. Example: 2005, workweek 10 = GJ

YEAR WORK

WEEK

CODE YEAR WORK

WEEK

CODE YEAR WORK

WEEK

CODE

2003 1

2004 1

2005 1

2006 1

2007 1

2008 1

2009 1

2010 1

2011 1

2012 1

2013 1

2014 1

2015 1

2016 1

2017 1

For dates outside of the table: the first character of the code is incremented at the start of workweek 01 and workweek 27

each year. The second character begins with “A” in workweek 01 of each year and increments weekly. “A” follows “Z” to make

the code continuous.

P1-P3 P4-P6 P7-P7

TCP-5056UB-DT

Mfr. #:

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Manufacturer:

ON Semiconductor

Description:

Tuners WLCSP6 5.6PF HIGH Q PTIC

Lifecycle:

New from this manufacturer.

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