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LTC3406ES5#TRPBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
10
LTC34 06
LTC34 06 -1.5/LTC34 06 -1.8
3406fa
APPLICATIO S I FOR ATIO
WUUU
Although all dissipative elements in the circuit produce
losses, two main sources usually account for most of the
losses in LTC3406 circuits: V
IN
quiescent current and I
2
R
losses. The V
IN
quiescent current loss dominates the
efficiency loss at very low load currents whereas the I
2
R
loss dominates the efficiency loss at medium to high load
currents. In a typical efficiency plot, the efficiency curve at
very low load currents can be misleading since the actual
power lost is of no consequence as illustrated in Figure 4.
2. I
2
R losses are calculated from the resistances of the
internal switches, R
SW
, and external inductor R
L
. In
continuous mode, the average output current flowing
through inductor L is “chopped” between the main
switch and the synchronous switch. Thus, the series
resistance looking into the SW pin is a function of both
top and bottom MOSFET R
DS(ON)
and the duty cycle
(DC) as follows:
R
SW
= (R
DS(ON)TOP
)(DC) + (R
DS(ON)BOT
)(1 – DC)
The R
DS(ON)
for both the top and bottom MOSFETs can
be obtained from the Typical Performance Charateristics
curves. Thus, to obtain I
2
R losses, simply add R
SW
to
R
L
and multiply the result by the square of the average
output current.
Other losses including C
IN
and C
OUT
ESR dissipative
losses and inductor core losses generally account for less
than 2% total additional loss.
Thermal Considerations
In most applications the LTC3406 does not dissipate
much heat due to its high efficiency. But, in applications
where the LTC3406 is running at high ambient tempera-
ture with low supply voltage and high duty cycles, such
as in dropout, the heat dissipated may exceed the maxi-
mum junction temperature of the part. If the junction
temperature reaches approximately 150°C, both power
switches will be turned off and the SW node will become
high impedance.
To avoid the LTC3406 from exceeding the maximum
junction temperature, the user will need to do some
thermal analysis. The goal of the thermal analysis is to
determine whether the power dissipated exceeds the
maximum junction temperature of the part. The tempera-
ture rise is given by:
T
R
= (P
D
)(θ
JA
)
where P
D
is the power dissipated by the regulator and θ
JA
is the thermal resistance from the junction of the die to the
ambient temperature.
Figure 4. Power Lost vs Load Current
1. The V
IN
quiescent current is due to two components:
the DC bias current as given in the electrical character-
istics and the internal main switch and synchronous
switch gate charge currents. The gate charge current
results from switching the gate capacitance of the
internal power MOSFET switches. Each time the gate is
switched from high to low to high again, a packet of
charge, dQ, moves from V
IN
to ground. The resulting
dQ/dt is the current out of V
IN
that is typically larger than
the DC bias current. In continuous mode, I
GATECHG
=
f(Q
T
+ Q
B
) where Q
T
and Q
B
are the gate charges of the
internal top and bottom switches. Both the DC bias and
gate charge losses are proportional to V
IN
and thus
their effects will be more pronounced at higher supply
voltages.
LOAD CURRENT (mA)
0.1 1
0.00001
POWER LOSS (W)
0.001
1
10 100 1000
3406 F04
0.0001
0.01
0.1
V
OUT
= 1.2V
V
OUT
= 1.5V
V
OUT
= 1.8V
V
OUT
= 2.5V
11
LTC34 06
LTC34 0 6 -1.5/LTC34 0 6 -1.8
3406fa
APPLICATIO S I FOR ATIO
WUUU
The junction temperature, T
J
, is given by:
T
J
= T
A
+ T
R
where T
A
is the ambient temperature.
As an example, consider the LTC3406 in dropout at an
input voltage of 2.7V, a load current of 600mA and an
ambient temperature of 70°C. From the typical perfor-
mance graph of switch resistance, the R
DS(ON)
of the
P-channel switch at 70°C is approximately 0.52Ω. There-
fore, power dissipated by the part is:
P
D
= I
LOAD
2
• R
DS(ON)
= 187.2mW
For the SOT-23 package, the θ
JA
is 250°C/W. Thus, the
junction temperature of the regulator is:
T
J
= 70°C + (0.1872)(250) = 116.8°C
which is below the maximum junction temperature of
125°C.
Note that at higher supply voltages, the junction tempera-
ture is lower due to reduced switch resistance (R
DS(ON)
).
Checking Transient Response
The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, V
OUT
immediately shifts by an amount
equal to (∆I
LOAD
• ESR), where ESR is the effective series
resistance of C
OUT
. ∆I
LOAD
also begins to charge or
discharge C
OUT
, which generates a feedback error signal.
The regulator loop then acts to return V
OUT
to its steady-
state value. During this recovery time V
OUT
can be moni-
tored for overshoot or ringing that would indicate a stability
problem. For a detailed explanation of switching control
loop theory, see Application Note 76.
A second, more severe transient is caused by switching in
loads with large (>1µF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with C
OUT
, causing a rapid drop in V
OUT
. No regulator can
deliver enough current to prevent this problem if the load
switch resistance is low and it is driven quickly. The only
solution is to limit the rise time of the switch drive so that
the load rise time is limited to approximately (25 • C
LOAD
).
Thus, a 10µF capacitor charging to 3.3V would require a
250µs rise time, limiting the charging current to about
130mA.
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3406. These items are also illustrated graphically in
Figures 5 and 6. Check the following in your layout:
1. The power traces, consisting of the GND trace, the SW
trace and the V
IN
trace should be kept short, direct and
wide.
2. Does the V
FB
pin connect directly to the feedback
resistors? The resistive divider R1/R2 must be con-
nected between the (+) plate of C
OUT
and ground.
3. Does the (+) plate of C
IN
connect to V
IN
as closely as
possible? This capacitor provides the AC current to the
internal power MOSFETs.
4. Keep the switching node, SW, away from the sensitive
V
FB
node.
5. Keep the (–) plates of C
IN
and C
OUT
as close as possible.
12
LTC34 06
LTC34 06 -1.5/LTC34 06 -1.8
3406fa
APPLICATIO S I FOR ATIO
WUUU
Design Example
As a design example, assume the LTC3406 is used in a
single lithium-ion battery-powered cellular phone
application. The V
IN
will be operating from a maximum of
4.2V down to about 2.7V. The load current requirement
is a maximum of 0.6A but most of the time it will be in
standby mode, requiring only 2mA. Efficiency at both low
and high load currents is important. Output voltage is
2.5V. With this information we can calculate L using
equation (1),
L
fI
V
V
V
L
OUT
OUT
IN
=
()
∆
()
−
⎛
⎝
⎜
⎞
⎠
⎟
1
1
(3)
Figure 5a. LTC3406 Layout Diagram
Figure 6a. LTC3406 Suggested Layout
Substituting V
OUT
= 2.5V, V
IN
= 4.2V, ∆I
L
= 240mA and
f = 1.5MHz in equation (3) gives:
L
V
MHz mA
V
V
H= −
⎛
⎝
⎜
⎞
⎠
⎟
=µ
25
1 5 240
1
25
42
281
.
.( )
.
.
.
A 2.2µH inductor works well for this application. For best
efficiency choose a 720mA or greater inductor with less
than 0.2Ω series resistance.
C
IN
will require an RMS current rating of at least 0.3A ≅
I
LOAD(MAX)
/2 at temperature and C
OUT
will require an ESR
of less than 0.25Ω. In most cases, a ceramic capacitor will
satisfy this requirement.
RUN
LTC3406
GND
SW
L1
R2
R1
C
FWD
BOLD LINES INDICATE HIGH CURRENT PATHS
V
IN
V
OUT
3406 F05a
4
5
1
3
+
–
2
V
FB
V
IN
C
IN
C
OUT
RUN
LTC3406-1.8
GND
SW
L1
BOLD LINES INDICATE HIGH CURRENT PATHS
V
IN
V
OUT
3406 F05b
4
5
1
3
+
–
2
V
OUT
V
IN
C
IN
C
OUT
Figure 5b. LTC3406-1.8 Layout Diagram
LTC3406
GND
3406 F06a
PIN 1
V
OUT
V
IN
VIA TO V
OUT
SW
VIA TO V
IN
VIA TO GND
C
OUT
C
IN
L1
R2
C
FWD
R1
LTC3406-1.8
GND
3406 F06b
PIN 1
V
OUT
V
IN
SW
VIA TO V
IN
VIA TO V
OUT
C
OUT
C
IN
L1
Figure 6b. LTC3406-1.8 Suggested Layout
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

LTC3406ES5#TRPBF

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Buy LTC3406ES5#TRPBF
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators 600mA, 1.5MHz Sync Step-dwn in ThinSOT
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