Philips Semiconductors Product specification
74ALVCH1682518-bit buffer/driver (3-State)
2
1998 Jul 27 853-2097 19785
FEATURES
• Wide supply voltage range of 1.2V to 3.6V
• Complies with JEDEC standard no. 8-1A.
• CMOS low power consumption
• Direct interface with TTL levels
• Current drive ± 24 mA at 3.0 V
• MULTIBYTE
TM
flow-through standard pin-out architecture
• Low inductance multiple V
CC
and GND pins for minimum noise
and ground bounce
• All data inputs have bus hold
• Output drive capability 50Ω transmission lines @ 85°C
DESCRIPTION
The 74ALVCH16825 is an 18–bit non-inverting buffer/driver with
3-State outputs for bus-oriented applications.
The 74ALVCH16825 consists of two 9-bit sections with separate
output enable signals. For either 9-bit buffer section, the two output
enable (1OE
1 and 1OE2 or 2OE1 and 2OE2) inputs must both be
LOW for corresponding D outputs to be active. If either output
enable input is HIGH, the outputs of that 9-buffer section are in the
high impedance state.
The 74ALVCH16825 has active bus hold circuitry which is provided
to hold unused or floating data inputs at a valid logic level. This
feature eliminates the need for external pull-up or pull-down
resistors.
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28 29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
561OE1
1Y
1
1Y
1
1Y
2
1Y
3
1Y
4
1Y
5
1Y
6
GND
V
CC
GND
1Y
7
1Y
8
GND
GND
2Y
0
2Y
1
GND
2Y
2
2Y
3
2Y
4
V
CC
2Y
5
2Y
6
GND
2Y
7
2OE1
1A
0
1A
1
GND
1A
2
1A
3
V
CC
1A
4
1A
5
1A
6
GND
1A
7
1A
8
GND
GND
2A
0
2A
1
GND
2A
2
2A
3
2A
4
V
CC
2A
5
2A
6
GND
2A
7
2A
8
2Y
8
2OE2
1OE
2
SH00139
QUICK REFERENCE DATA
GND = 0V; T
amb
= 25°C; t
r
= t
f
≤ 2.5ns
SYMBOL
PARAMETER CONDITIONS TYPICAL UNIT
t
PHL
/t
PLH
Propagation delay
CP to Qn
V
CC
= 2.5V, C
L
= 30pF
V
CC
= 3.3V, C
L
= 50pF
2.0
2.0
ns
C
I
Input capacitance 4.0 pF
p
p
p
Output enabled 19
p
PD
I
=
CC
Output disabled 3
NOTES:
1. C
PD
is used to determine the dynamic power dissipation (P
D
in µW):
P
D
= C
PD
× V
CC
2
× f
i
+ (C
L
× V
CC
2
× f
o
) where: f
i
= input frequency in MHz; C
L
= output load capacitance in pF;
f
o
= output frequency in MHz; V
CC
= supply voltage in V; (C
L
× V
CC
2
× f
o
) = sum of outputs.
ORDERING INFORMATION
PACKAGES
TEMPERATURE
RANGE
OUTSIDE NORTH
AMERICA
NORTH AMERICA
DRAWING
NUMBER
56-Pin Plastic Thin Shrink Small Outline (TSSOP) Type II –40°C to +85°C 74ALVCH16825 DGG ACH16825 DGG SOT364-1
