OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

MAX2121ETI+

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19
MAX2121
Complete Direct-Conversion L-Band Tuner
10
Detailed Description
Register Description
The MAX2121 includes 12 user-programmable registers
and two read-only registers. See Table 1 for register
configurations. The register configuration of Table 1
shows each bit name and the bit usage information for all
registers. Note that all registers must be written after and
no earlier than 100µs after the device is powered up. The
VCO autoselection circuit is triggered by writing to regis-
ter 5. Thus register 5 should be the last register to be
written in order to ensure proper PLL lock.
Table 1. Register Configuration
MSB LSB
DATA BYTE
REG
NUMBER
REGISTER
NAME
READ/
WRITE
REG
ADDRESS
D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
1
N-Divider
MSB
Write 0x00
FRAC
1
N[14] N[13] N[12] N[11] N[10] N[9] N[8]
2
N-Divider
LSB
Write 0x01 N[7] N[6] N[5] N[4] N[3] N[2] N[1] N[0]
3
Charge
Pump
Write 0x02
CPMP[1]
0
CPMP[0]
0
CPLIN[1]
0
CPLIN[0]
1
F[19] F[18] F[17] F[16]
4
F-Divider
MSB
Write 0x03 F[15] F[14] F[13] F[12] F[11] F[10] F[9] F[8]
5
F-Divider
LSB
Write 0x04 F[7] F[6] F[5] F[4] F[3] F[2] F[1] F[0]
6
XTAL
Buffer and
Reference
Divider
Write 0x05 XD[2] XD[1] XD[0] R[4] R[3] R[2] R[1] R[0]
7 PLL Write 0x06 D24 CPS ICP X X X X X
8 VCO Write 0x07 VCO[4] VCO[3] VCO[2] VCO[1] VCO[0] VAS ADL ADE
9
Lowpass
Filter
Write 0x08 10010111
10 Control Write 0x09 STBY X
PWDN
0
X BBG[3] BBG[2] BBG[1] BBG[0]
11 Shutdown Write 0x0A X
PLL
0
DIV
0
VCO
0
BB
0
RFMIX
0
RFVGA
0
FE
0
12 Test Write 0x0B
CPTST[2]
0
CPTST[1]
0
CPTST[0]
0
X
TURBO
1
LD
MUX[2]
0
LD
MUX[1]
0
LD
MUX[0]
0
13
Status
Byte-1
Read 0x0C POR VASA VASE LD X X X X
14
Status
Byte-2
Read 0x0D VCOSBR[4] VCOSBR[3] VCOSBR[2] VCOSBR[1] VCOSBR[0] ADC[2] ADC[1] ADC[0]
X = Don’t care. 0 = Set to 0 for factory-tested operation. 1 = Set to 1 for factory-tested operation.
MAX2121
Complete Direct-Conversion L-Band Tuner
11
Table 2. N-Divider MSB Register (Address: 0x00)
BIT NAME BIT LOCATION (0 = LSB) DEFAULT FUNCTION
FRAC 7 1 Users must program to 1 upon powering up the device.
N[14:8] 6–0 0000000
Sets the most significant bits of the PLL integer-divide number (N). N can
range from 19 to 251.
Table 3. N-Divider LSB Register (Address: 0x01)
BIT NAME BIT LOCATION (0 = LSB) DEFAULT FUNCTION
N[7:0] 7–0 00100011
Sets the least significant bits of the PLL integer-divide number. N can range
from 19 to 251.
Table 4. Charge-Pump Register (Address: 0x02)
BIT NAME BIT LOCATION (0 = LSB) DEFAULT FUNCTION
CPMP[1:0] 7–6 00
Charge-pump minimum pulse width. Users must program to 00 upon
powering up the device.
CPLIN[1:0] 5–4 00
Controls charge-pump linearity. Users must program to 01 upon powering
up the device.
F[19:16] 3–0 0010
Sets the 4 most significant bits of the PLL fractional divide number.
Default value is F = 194,180 decimal.
Table 5. F-Divider MSB Register (Address: 0x03)
BIT NAME BIT LOCATION (0 = LSB) DEFAULT FUNCTION
F[15:8] 7–0 11110110
Sets the most significant bits of the PLL fractional-divide number (F).
Default value is F = 194,180 decimal.
Table 6. F-Divider LSB Register (Address: 0x04)
BIT NAME BIT LOCATION (0 = LSB) DEFAULT FUNCTION
F[7:0] 7–0 10000100
Sets the least significant bits of the PLL fractional-divide number (F).
Default value is F = 194,180 decimal.
Table 7. XTAL Buffer and Reference Divider Register (Address: 0x05)
BIT NAME BIT LOCATION (0 = LSB) DEFAULT FUNCTION
XD[2:0] 7–5 000
Sets the crystal-divider setting.
000 = Divide by 1.
001 = Divide by 2.
011 = Divide by 3.
100 = Divide by 4.
101 through 110 = All divide values from 5 (101) to 7 (110).
111 = Divide by 8.
R[4:0] 4–0 00001
Sets the PLL reference-divider (R) number. Users must program to 00001
upon powering up the device.
00001 = Divide by 1; other values are not tested.
MAX2121
Complete Direct-Conversion L-Band Tuner
12
Table 8. PLL Register (Address: 0x06)
BIT NAME BIT LOCATION (0 = LSB) DEFAULT FUNCTION
D24 7 1
VCO divider setting.
0 = Divide by 2. Use for LO frequencies 1125MHz.
1 = Divide by 4. Use for LO frequencies < 1125MHz.
CPS 6 1
Charge-pump current mode.
0 = Charge-pump current controlled by ICP bit.
1 = Charge-pump current controlled by VCO autoselect (VAS).
ICP 5 0
Charge-pump current.
0 = 600µA typical.
1 = 1200µA typical.
X 4–0 X Don’t care.
Table 9. VCO Register (Address: 0x07)
BIT NAME BIT LOCATION (0 = LSB) DEFAULT FUNCTION
VCO[4:0] 7–3 11001
Controls which VCO is activated when using manual VCO programming mode.
This also serves as the starting point for the VCO autoselection (VAS) mode.
VAS 2 1
VCO autoselection (VAS) circuit.
0 = Disable VCO selection must be programmed through I
2
C.
1 = Enable VCO selection controlled by autoselection circuit.
ADL 1 0
Enables or disables the VCO tuning voltage ADC latch when the VCO
autoselect mode (VAS) is disabled.
0 = Disables the ADC latch.
1 = Latches the ADC value.
ADE 0 0
Enables or disables VCO tuning voltage ADC read when the VCO
autoselect mode (VAS) is disabled.
0 = Disables ADC read.
1 = Enables ADC read.
Table 10. Lowpass Filter Register (Address: 0x08)
BIT NAME BIT LOCATION (0 = LSB) DEFAULT FUNCTION
Reserved 7–0 01001011 User must program to 10010111 (97h) upon powering up the device.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19

MAX2121ETI+

Mfr. #:
Buy MAX2121ETI+
Manufacturer:
Maxim Integrated
Description:
Tuners Direct-Conversion L-Band Tuner
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet