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NLV74VHCT32ADTR2G

P1-P3P4-P6P7-P7
© Semiconductor Components Industries, LLC, 2011
May, 2011 − Rev. 4
1 Publication Order Number:
MC74VHCT32A/D
MC74VHCT32A
Quad 2-Input OR Gate /
CMOS Logic Level Shifter
with LSTTL − Compatible Inputs
The MC74VHCT32A is an advanced high speed CMOS 2−input
OR gate fabricated with silicon gate CMOS technology. It achieves
high speed operation similar to equivalent Bipolar Schottky TTL
while maintaining CMOS low power dissipation.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output.
The device input is compatible with TTL−type input thresholds and
the output has a full 5.0 V CMOS level output swing. The input
protection circuitry on this device allows overvoltage tolerance on the
input, allowing the device to be used as a logic−level translator from
3.0 V CMOS logic to 5.0 V CMOS Logic or from 1.8 V CMOS logic
to 3.0 V CMOS Logic while operating at the high−voltage power
supply.
The MC74VHCT32A input structure provides protection when
voltages up to 7.0 V are applied, regardless of the supply voltage. This
allows the MC74VHCT32A to be used to interface 5.0 V circuits to
3.0 V circuits. The output structures also provide protection when
V
CC
= 0 V. These input and output structures help prevent device
destruction caused by supply voltage − input/output voltage mismatch,
battery backup, hot insertion, etc.
Features
• High Speed: t
PD
= 3.8 ns (Typ) at V
CC
= 5.0 V
• Low Power Dissipation: I
CC
= 2 mA (Max) at T
A
= 25°C
• TTL−Compatible Inputs: V
IL
= 0.8 V; V
IH
= 2.0 V
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
• Designed for 2.0 V to 5.5 V Operating Range
• Low Noise: V
OLP
= 0.8 V (Max)
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300 mA
• ESD Performance:
Human Body Model > 2000 V;
Machine Model > 200 V
• These Devices are Pb−Free and are RoHS Compliant
TSSOP−14
DT SUFFIX
CASE 948G
SOEIAJ−14
M SUFFIX
CASE 965
http://onsemi.com
74VHCT32
ALYWG
1
VHCT32AG
AWLYWW
1
14
SOIC−14
D SUFFIX
CASE 751A
†For additional marking information, refer to
Application Note AND8002/D.
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
ORDERING INFORMATION
MARKING
DIAGRAMS
†
1
VHCT
32A
ALYW
1
14
1
14
1
A = Assembly Location
WL, L = Wafer Lot
Y = Year
WW, W = Work Week
G or = Pb−Free Package
(Note: Microdot may be in either location)
MC74VHCT32A
http://onsemi.com
2
3
Y1
1
A1
2
B1
6
Y2
4
A2
5
B2
8
Y3
9
A3
10
B3
11
Y4
12
A4
13
B4
Y = A)
B
Figure 1. Pin Connection and Marking Diagram (Top View)
1314 12 11 10 9 8
21 34567
V
CC
B4 A4 Y4 B3 A3 Y3
A1 B1 Y1 A2 B2 Y2 GND
Figure 2. Logic Diagram
Table 1. FUNCTION TABLE
Inputs Output
A B Y
L
L
H
H
L
H
L
H
L
H
H
H
MAXIMUM RATINGS
Symbol Parameter Value Unit
V
CC
DC Supply Voltage –0.5 to +7.0 V
V
in
DC Input Voltage –0.5 to +7.0 V
V
out
DC Output Voltage V
CC
= 0
High or Low State
–0.5 to +7.0
–0.5 to V
CC
+ 0.5
V
I
IK
Input Diode Current −20 mA
I
OK
Output Diode Current (V
OUT
< GND; V
OUT
> V
CC
) ±20 mA
I
out
DC Output Current, per Pin ±25 mA
I
CC
DC Supply Current, V
CC
and GND Pins ±50 mA
P
D
Power Dissipation in Still Air, SOIC Packages†
TSSOP Package†
500
450
mW
T
stg
Storage Temperature –65 to +150 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
NOTE: This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However,
precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance
circuit. For proper operation, V
in
and V
out
should be constrained to the range GND v (V
in
or V
out
) v V
CC
. Unused inputs must
always be tied to an appropriate logic voltage level (e.g., either GND or V
CC
). Unused outputs must be left open.
†Derating − SOIC Packages: – 7 mW/°C from 65° to 125°C
TSSOP Package: − 6.1 mW/°C from 65° to 125°C
MC74VHCT32A
http://onsemi.com
3
RECOMMENDED OPERATING CONDITIONS
Symbol Characteristics Min Max Unit
V
CC
DC Supply Voltage 2.0 5.5 V
V
IN
DC Input Voltage 0.0 5.5 V
V
OUT
DC Output Voltage V
CC
= 0
High or Low State
0.0
0.0
5.5
V
CC
V
T
A
Operating Temperature Range −55 +125 °C
t
r
, t
f
Input Rise and Fall Time V
CC
= 3.3V ± 0.3V
V
CC
= 5.0V ± 0.5V
0
0
100
20
ns/V
NOISE CHARACTERISTICS (Input t
r
= t
f
= 3.0 ns, C
L
= 50 pF, V
CC
= 5.0 V)
Symbol
Characteristic
T
A
= 25°C
Unit
Typ Max
V
OLP
Quiet Output Maximum Dynamic V
OL
0.3 0.8 V
V
OLV
Quiet Output Minimum Dynamic V
OL
− 0.3 − 0.8 V
V
IHD
Minimum High Level Dynamic Input Voltage 3.5 V
V
ILD
Maximum Low Level Dynamic Input Voltage 1.5 V
DC ELECTRICAL CHARACTERISTICS
Symbol Parameter Test Conditions
V
CC
T
A
= 25°C T
A
≤ 85°C T
A
≤ 125°C
Unit
(V) Min Typ Max Min Max Min Max
V
IH
Minimum High−Level Input
Voltage
3.0
4.5
5.5
1.2
2.0
2.0
1.2
2.0
2.0
1.2
2.0
2.0
V
V
IL
Maximum Low−Level Input
Voltage
3.0
4.5
5.5
0.53
0.8
0.8
0.53
0.8
0.8
0.53
0.8
0.8
V
V
OH
Minimum High−Level Output
Voltage V
IN
= V
IH
or V
IL
V
IN
= V
IH
or V
IL
I
OH
= −50 mA
3.0
4.5
2.9
4.4
3.0
4.5
2.9
4.4
2.9
4.4
V
V
IN
= V
IH
or V
IL
I
OH
= −4 mA
I
OH
= −8 mA
3.0
4.5
2.58
3.94
2.48
3.80
2.34
3.66
V
V
OL
Maximum Low−Level Output
Voltage V
IN
= V
IH
or V
IL
V
IN
= V
IH
or V
IL
I
OL
= 50 mA
3.0
4.5
0.0
0.0
0.1
0.1
0.1
0.1
0.1
0.1
V
V
IN
= V
IH
or V
IL
I
OL
= 4 mA
I
OL
= 8 mA
3.0
4.5
0.36
0.36
0.44
0.44
0.52
0.52
V
I
IN
Maximum Input Leakage
Current
V
IN
= 5.5 V or GND 0 to
5.5
±0.1 ±1.0 ±1.0
mA
I
CC
Maximum Quiescent Supply
Current
V
IN
= V
CC
or GND 5.5 2.0 20 40
mA
I
CCT
Quiescent Supply Current Input: V
IN
= 3.4 V 5.5 1.35 1.50 1.65 mA
I
OPD
Output Leakage Current V
OUT
= 5.5 V 0.0 0.5 5.0 10
mA
P1-P3P4-P6P7-P7

NLV74VHCT32ADTR2G

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Manufacturer:
ON Semiconductor
Description:
Logic Gates LOG CMOS GATE OR
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