Component Selection Procedure
• Determine load capacitance:
C
L
= C2 + C3 + module input capacitance
• Determine load current, I
LOAD
.
• Select circuit-breaker current; for example:
I
CB
= 2 x I
LOAD
• Calculate R
SENSE
:
Realize that I
CB
varies ±20% due to trip-voltage
tolerance.
• Set allowable inrush current:
• Determine value of C2:
• Calculate value of C1:
• Determine value of R3:
• Set R2 = 10Ω.
• If an optocoupler is utilized as in Figure 15, deter-
mine the LED series resistor:
Although the suggested optocoupler is not specified for
operation below 5mA, its performance is adequate for
36V temporary low-line voltage where LED current
would then be ≈2.2mA to 3.7mA. If R7 is set as high as
51kΩ, optocoupler operation should be verified over
the expected temperature and input voltage range to
ensure suitable operation when LED current ≈0.9mA for
48V input and ≈0.7mA for 36V input.
If input transients are expected to momentarily raise the
input voltage to >100V, select an input transient-volt-
age-suppression diode (TVS) to limit maximum voltage
on the MAX5949 to less than 100V. A suitable device is
the Diodes Inc. SMAT70A telecom-specific TVS.
Select Q1 to meet supply voltage, load current, efficien-
cy, and Q1 package power-dissipation requirements:
BV
DSS
≥ 100V
I
D(ON)
≥ 3x I
LOAD
DPAK, D
2
PAK, or TO-220AB
The lowest practical R
DS(ON)
, within budget constraints
and with values from 14mΩ to 540mΩ, are available at
100V breakdown.
Ensure that the temperature rise of Q1 junction is not
excessive at normal load current for the package select-
ed. Ensure that I
CB
current during voltage transients
does not exceed allowable transient-safe operating-area
limitations. This is determined from the SOA and tran-
sient-thermal-resistance curves in the Q1 manufacturer’s
data sheet.
Example 1:
I
LOAD
= 2.5A, efficiency = 98%, then V
DS
= 0.96V is
acceptable, or R
DS(ON)
≤ 384mΩ at operating temper-
ature is acceptable. An IRL520NS 100V NMOS with
R
DS(ON)
≤ 180mΩ and I
D(ON)
= 10A is available in
D
2
PAK. (A Vishay Siliconix SUD40N10-25 100V NMOS
with R
DS(ON)
≤ 25mΩ and I
D(ON)
= 40A is available in
DPAK, but may be more costly because of a larger die
size.)
Using the IRL520NS, V
DS
≤ 0.625V even at +80°C so
efficiency ≥ 98.6% at 80°C. P
D
≤ 1.56W and junction
temperature rise above case temperature would be 5°C
due to the package θ
JC
= 3.1°C/W thermal resistance.
Of course, using the SUD40N10-25 would yield an effi-
ciency greater than 99.8% to compensate for the
increased cost.
.
.