9397 750 13556 © Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet Rev. 01 — 22 September 2005 5 of 17
Philips Semiconductors
GTL2009
3-bit GTL Front-Side Bus frequency comparator
7.2 Default conditions input
The FSB GTL output data is masked and a specific default value (100 MHz) is inserted
upon power-up when V
DD
is greater than 1.5 V. The FSB GTL output data is unmasked
and valid data is supplied when the VREF input crosses a static 0.6 V internally generated
input comparator reference voltage. For slowly rising GTL V
TT
supply (0.7 V/500 µs), the
switch-over happens at the 0.6 V threshold. For fast rising GTL V
TT
supply (0.7 V/100 ns),
the switch-over typically occurs between 350 ns to 1.5 µs after the 0.6 V threshold is
exceeded.
The AO1 and AO2 outputs do not have ‘default conditions’ like those assigned to the GTL
outputs. Instead, these two pins will power-up according to the conditions applied to the
1A1 and 2A1 input pins as shown in Table 8. If the slot is occupied, the input is LOW.
It is important to note that the AO1 and AO2 outputs may be valid a little before 1.5 V and
will rise with V
DD
. Valid outputs from the system level perspective will be achieved after
V
DD
is in regulation, V
TT
ramps up, and after the internal propagation delay of the
GTL2009. No firm answer for this can be given since the time it takes for V
DD
to be in
regulation varies from 100 ms to 1000 ms, and the rise time of V
TT
is unknown. The
GTL2009 outputs are valid after the GTL inputs are valid plus 19.6 ns (worst-case
propagation delay of the GTL-to-LVTTL path).
Table 8: AO1 and AO2 power-up conditions
H = HIGH; L = LOW.
1AI 2AI V
DD
AO1 AO2
L L <1.5 V L L
L L >1.5 V H H
L H <1.5 V L L
L H >1.5 V L L
H L <1.5 V L L
H L >1.5 V L H
H H <1.5 V L L
H H >1.5 V H H
