IDT5P50911/2/3/4
SPREAD SPECTRUM CLOCK SYNTHESIZER CLOCK SYNTHESIZER
IDT®
SPREAD SPECTRUM CLOCK SYNTHESIZER 3
IDT5P50911/2/3/4 REV D 070214
External Components
Decoupling Capacitor
As with any high-performance mixed-signal IC, the
IDT5P50911/2/3/4 must be isolated from system power
supply noise to perform optimally.
A decoupling capacitor of 0.01µF must be connected
between each VDD and the PCB ground plane.
Series Termination Resistor
Clock output traces over one inch should use series
termination. To series terminate a 50 trace (a commonly
used trace impedance), place a 33 resistor in series with
the clock line, as close to the clock output pin as possible.
The nominal impedance of the clock output is 20.
Crystal Load Capacitors
The device crystal connections should include pads for
small capacitors from X1 to ground and from X2 to ground.
These capacitors are used to adjust the stray capacitance of
the board to match the nominally required crystal load
capacitance. Because load capacitance can only be
increased in this trimming process, it is important to keep
stray capacitance to a minimum by using very short PCB
traces (and no vias) between the crystal and device. Crystal
capacitors, if needed, must be connected from each of the
pins X1 and X2 to ground.
The value (in pF) of these crystal caps should equal (C
L
-12
pF)*2. In this equation, C
L
= crystal load capacitance in pF.
Example: For a crystal with a 16 pF load capacitance, each
crystal capacitor would be 8 pF [(16-12) x 2 = 8].
PCB Layout Recommendations
For optimum device performance and lowest output phase
noise, the following guidelines should be observed.
1) The 0.01µF decoupling capacitors should be mounted on
the component side of the board as close to the VDD pin as
possible. No vias should be used between the decoupling
capacitors and VDD pins. The PCB trace to VDD pins
should be kept as short as possible, as should the PCB
trace to the ground via.
2) To minimize EMI, the 33 series termination resistor (if
needed) should be placed close to the clock output.
3) An optimum layout is one with all components on the
same side of the board, minimizing vias through other signal
layers. Other signal traces should be routed away from the
IDT5P50911/2/3/4. This includes signal traces just
underneath the device, or on layers adjacent to the ground
plane layer used by the device.
Spread Spectrum Profile
The IDT5P50911/2/3/4 is a low EMI clock generator using
an optimized frequency slew rate algorithm to facilitate down
stream tracking of zero delay buffers and other PLL devices.
The modulation rate is directly relate to the input crystal
frequency.
For input frequency ICLK, then use the modulation
frequency indicated for the part below.
Modulation Frequency = Input Frequency/10000
Ex. Input Frequency = 20 MHz
Modulation Frequency = 20 MHz/10000 = 2 kHz
Time
Frequency
Modulation Rate
