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650R-27ILF

P1-P3P4-P6P7-P7
DATASHEET
NETWORKING CLOCK SOURCE ICS650-27
IDT™ / ICS™
NETWORKING CLOCK SOURCE 1
ICS650-27 REV F 051310
Description
The ICS650-27 is a low cost, low jitter, high performance
clock synthesizer for networking applications. Using analog
Phase-Locked Loop (PLL) techniques, the device accepts a
12.5 MHz or 25 MHz clock or fundamental mode crystal
input to produce multiple output clocks for networking chips,
PCI devices, SDRAM, and ASICs. The ICS650-27 outputs
all have zero ppm synthesis error.
The ICS650-27 is pin compatible and functionally
equivalent to the ICS650-07. It is a performance
upgrade and is recommended for all new 3.3V designs.
See the MK74CB214, ICS551, and ICS552-01 for non-PLL
buffer devices which produce multiple low-skew copies of
these output clocks.
See the ICS570, ICS9112-16/17/18 for zero delay buffers
that can synchronize outputs and other needed clocks.
Features
• Packaged in 20-pin (150 mil) SSOP (QSOP)
• Pb (lead) free package, RoHS compliant
• 12.5 MHz or 25 MHz fundamental crystal or clock input
• Six output clocks with selectable frequencies
• SDRAM frequencies of 67, 83, 100, and 133 MHz
• Buffered crystal reference output
• Zero ppm synthesis error in all clocks
• Ideal for PMC-Sierra’s ATM switch chips
• Full CMOS output swing with 25 mA output drive
capability at TTL levels
• Advanced, low-power, sub-micron CMOS process
• Operating voltage of 3.3 V
• Industrial temperature only
Block Diagram
Clock
Buffer/
Crystal
Oscillator
Clock
Synthesis
and Control
Circuitry
25 or 12.5 MHz
cyrstal or clock
ACS1:0
CLKA1
CCS
GND
2
BCS1:0
2
2
X1/ICLK
X2
CLKA2
CLKB1
CLKB2
CLKC1
CLKC2
REFOUT
VDD
2
/2
/2
OE (all outputs)
ICS650-27
NETWORKING CLOCK SOURCE CLOCK SYNTHESIZER
IDT™ / ICS™
NETWORKING CLOCK SOURCE 2
ICS650-27 REV F 051310
Pin Assignment
Pin Descriptions
13
4
12
5
11
ASC1
8
9
10
VDD
CLKC2
CLKA2
CCS
CLKB2 DC
17
16
CLKB1
3X1/ICLK
VDD CLKA1
18 REFOUT
1ASC0
X2 BCS0
20 BCS1
19
14
2
7
GND
CLKC1
OE
GND
156
20-pin (150 mil) SSOP
Pin
Number
Pin
Name
Pin
Type
Pin Description
1 ACS0 Input A clock select 0. Selects outputs on CLKA1 and CLKA2 per table on page 3.
2 X2 Input Crystal connection. Connect to a fundamental crystal or leave unconnected for a clock
input.
3 X1/ICLK Input Crystal connection. Connect to a fundamental crystal or clock input.
4 VDD Power Connect to +3.3 V or 5 V. Must be the same as pin 16.
5 ACS1 Input A clock select 1. Selects outputs on CLKA1 and CLKA2 per table on page 3. Internal
pull-up.
6 GND Power Connect to ground.
7 CLKC1 Output Output Clock C1. Depends on setting of CCS per table on page 3.
8 CLKC2 Output Output Clock C2. Depends on setting of CCS per table on page 3. Same as CLKC1.
9 CLKB2 Output Output Clock B2. Depends on setting of BCS1, 0 per table on page 3.
10 CLKB1 Output Output Clock B1. Depends on setting of BCS1, 0 per table on page 3.
11 CCS Input Clock C select pin. Selects outputs on CLKC1 and CLKC2 per table on page 3.
12 DC - Don’t connect. Do not connect anything to this pin.
13 CLKA2 Output Output Clock A2. Depends on setting of ACS1, 0 per table on page 3.
14 GND Power Connect to ground.
15 OE Input Output enable. Tri-states all outputs when low. Internal pull-up.
16 VDD Power Connect to +3.3 V or 5 V. Must be the same as pin 4.
17 CLKA1 Output Output Clock A1. Depends on setting of ACS1, 0 per table on page 3.
18 REFOUT Output Buffered reference clock output. Same frequency as crystal or clock input.
19 BCS0 Input B clock select 0. Selects outputs on CLKB1 and CLKB2 per table on page 3.
20 BCS1 Input B clock select 1. Selects outputs on CLKB1 and CLKB2 per table on page 3. Internal
pull-up.
ICS650-27
NETWORKING CLOCK SOURCE CLOCK SYNTHESIZER
IDT™ / ICS™
NETWORKING CLOCK SOURCE 3
ICS650-27 REV F 051310
For a 25 MHz fundamental crystal or clock input, the following four tables apply:
A Clocks Select Table (outputs in MHz)
C Clocks Select Table (outputs in MHz)
B Clocks Select Table (outputs in MHz)
Reference Output Clock Frequency (in MHz)
For a 12.5 MHz fundamental crystal or clock input, the following four tables apply:
A Clocks Select Table (outputs in MHz)
C Clocks Select Table (outputs in MHz)
B Clocks Select Table (outputs in MHz)
Reference Output Clock Frequency (in MHz)
0 = connect directly to GND
M = leave unconnected (automatically self biases to VDD/2)
1 = connect directly to VDD
ASC1 ASC0 CLKA1 CLKA2
00100off (low)
0 M Test Test
0175off (low)
1 0 33.3333 16.6667
1 M Test Test
1 1 66.6667 33.3333
CCS CLKC1 CLKC2
0 125 125
M Test Test
17575
BSC1 BSC0 CLKB1 CLKB2
0 0 Tes t Test
0 M 66.6667 33.3333
0110050
1 0 83.3333 41.6667
1 M Tes t Test
1 1 133.3333 66.6667
REFOUT
25
ASC1 ASC0 CLKA1 CLKA2
0050off (low)
0 M Test Test
0 1 37.5 off (low)
1 0 16.6667 8.3333
1 M Test Test
1 1 33.3333 16.6667
CCS CLKC1 CLKC2
0 62.5 62.5
M Test Test
1 37.5 37.5
BSC1 BSC0 CLKB1 CLKB2
0 0 Tes t Test
0 M 33.3333 16.6667
0 1 50 25
1 0 41.6667 20.8333
1 M Tes t Test
1 1 66.6667 33.3333
REFOUT
12.5
P1-P3P4-P6P7-P7

650R-27ILF

Mfr. #:
Buy 650R-27ILF
Manufacturer:
IDT
Description:
Clock Generators & Support Products SYSTEM PERIPHERAL CLOCK SOURCE
Lifecycle:
New from this manufacturer.
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