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ADC1610S125F2-DB

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P38
ADC1610S_SER 4 © IDT 2012. All rights reserved.
Product data sheet Rev. 04 — 2 July 2012 4 of 38
Integrated Device Technology
ADC1610S series
Single 16-bit ADC; CMOS or LVDS DDR digital output
[1] P: power supply; G: ground; I: input; O: output; I/O: input/output.
D15 17 O data output bit 15 (Most Significant Bit (MSB))
D14 18 O data output bit 14
D13 19 O data output bit 13
D12 20 O data output bit 12
D11 21 O data output bit 11
D10 22 O data output bit 10
D9 23 O data output bit 9
D8 24 O data output bit 8
D7 25 O data output bit 7
D6 26 O data output bit 6
D5 27 O data output bit 5
D4 28 O data output bit 4
D3 29 O data output bit 3
D2 30 O data output bit 2
D1 31 O data output bit 1
D0 32 O data output bit 0 (Least Significant Bit (LSB))
VDDO 33 P output power supply
DAV 34 O data valid output clock
n.c. 35 - not connected
SCLK/DFS 36 I SPI clock; data format select
SDIO/ODS 37 I/O SPI data IO; output data standard
CS
38 I SPI chip select
SENSE 39 I reference programming pin
VREF 40 I/O voltage reference input/output
Table 2. Pin description (CMOS digital outputs)
…continued
Symbol Pin Type
[1]
Description
ADC1610S_SER 4 © IDT 2012. All rights reserved.
Product data sheet Rev. 04 — 2 July 2012 5 of 38
Integrated Device Technology
ADC1610S series
Single 16-bit ADC; CMOS or LVDS DDR digital output
[1] Pins 1 to 16 and pins 36 to 40 are the same for both CMOS and LVDS DDR outputs (see Table 2).
[2] P: power supply; G: ground; I: input; O: output; I/O: input/output.
7. Limiting values
8. Thermal characteristics
[1] Value for six layers board in still air with a minimum of 25 thermal vias.
Table 3. Pin description (LVDS DDR) digital outputs)
Symbol Pin
[1]
Type
[2]
Description
D14_D15_M 17 O differential output data D14 and D15 multiplexed, complement
D14_D15_P 18 O differential output data D14 and D15 multiplexed, true
D12_D13_M 19 O differential output data D12 and D13 multiplexed, complement
D12_D13_P 20 O differential output data D12 and D13 multiplexed, true
D10_D11_M 21 O differential output data D10 and D11multiplexed, complement
D10_D11_P 22 O differential output data D10 and D11 multiplexed, true
D8_D9_M 23 O differential output data D8 and D9 multiplexed, complement
D8_D9_P 24 O differential output data D8 and D9 multiplexed, true
D6_D7_M 25 O differential output data D6 and D7 multiplexed, complement
D6_D7_P 26 O differential output data D6 and D7 multiplexed, true
D4_D5_M 27 O differential output data D4 and D5 multiplexed, complement
D4_D5_P 28 O differential output data D4 and D5 multiplexed, true
D2_D3_M 29 O differential output data D2 and D3 multiplexed, complement
D2_D3_P 30 O differential output data D2 and D3 multiplexed, true
D0_D1_M 31 O differential output data D0 and D1 multiplexed, complement
D0_D1_P 32 O differential output data D0 and D1 multiplexed, true
DAVM 34 O data valid output clock, complement
DAVP 35 O data valid output clock, true
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
V
O
output voltage pins D15 to D0;
pins D14_D15_P to D0_D1_P;
pins D14_D15_M to D0_D1_M
0.4 +3.9 V
V
DDA
analog supply voltage 0.4 +3.9 V
V
DDO
output supply voltage 0.4 +3.9 V
T
stg
storage temperature 55 +125 C
T
amb
ambient temperature 40 +85 C
T
j
junction temperature - 125 C
Table 5. Thermal characteristics
Symbol Parameter Conditions Typ Unit
R
th(j-a)
thermal resistance from junction to ambient
[1]
22.5 K/W
R
th(j-c)
thermal resistance from junction to case
[1]
11.7 K/W
ADC1610S_SER 4 © IDT 2012. All rights reserved.
Product data sheet Rev. 04 — 2 July 2012 6 of 38
Integrated Device Technology
ADC1610S series
Single 16-bit ADC; CMOS or LVDS DDR digital output
9. Static characteristics
Table 6. Static characteristics
[1]
Symbol Parameter Conditions Min Typ Max Unit
Supplies
V
DDA
analog supply voltage 2.85 3.0 3.4 V
V
DDO
output supply voltage CMOS mode 1.65 1.8 3.6 V
LVDS DDR mode 2.85 3.0 3.6 V
I
DDA
analog supply current f
clk
=125Msps; f
i
=70MHz - 210 - mA
I
DDO
output supply current CMOS mode;
f
clk
=125Msps; f
i
=70MHz
-14-mA
LVDS DDR mode:
f
clk
=125Msps; f
i
=70MHz
-43-mA
P power dissipation ADC1610S125;
analog supply only
-630-mW
ADC1610S105;
analog supply only
-550-mW
ADC1610S080;
analog supply only
-430-mW
ADC1610S065;
analog supply only
-380-mW
Power-down mode - 2 - mW
Sleep mode - 40 - mW
Clock inputs: pins CLKP and CLKM
Low-Voltage Positive Emitter-Coupled Logic (LVPECL)
V
i(clk)dif
differential clock input voltage peak-to-peak - 1.6 - V
SINE
V
i(clk)dif
differential clock input voltage peak - 3.0 - V
Low Voltage Complementary Metal Oxide Semiconductor (LVCMOS)
V
IL
LOW-level input voltage - - 0.3V
DDA
V
V
IH
HIGH-level input voltage 0.7V
DDA
--V
Logic inputs, Power-down: pin PWD/OE
V
IL
LOW-level input voltage - 0 - V
LOW-medium level - 0.3V
DDA
-V
Medium-HIGH level - 0.6V
DDA
-V
V
IH
HIGH-level input voltage - V
DDA
-V
I
IL
LOW-level input current - 55 - A
I
IH
HIGH-level input current - 65 - A
Serial peripheral interface: pins CS
, SDIO/ODS, SCLK/DFS
V
IL
LOW-level input voltage 0 - 0.3V
DDA
V
V
IH
HIGH-level input voltage 0.7V
DDA
-V
DDA
V
I
IL
LOW-level input current 10 - +10 A
I
IH
HIGH-level input current 50 - +50 A
C
I
input capacitance - 4 - pF
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P38

ADC1610S125F2-DB

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