AD215–Performance Characteristics
REV. 0
–6–
10
0%
100
90
5V
100mV
OUTPUT
INPUT
(+10V STEP)
OVERSHOOT
5µs
Figure 7a. Overshoot to a Full-Scale Step Input
(G = 1 V/V)
10
0%
100
90
5µs
5V
100mV
INPUT
(–10V STEP)
OUTPUT
UNDERSHOOT
Figure 7b. Undershoot to a Full-Scale Input
(G = 1 V/V)
10
0%
100
90
10µs
5V
±10V, 15kHz STEP OUTPUT RESPONSE (G=1)
Figure 8. Output Response to Full-Scale Step Input
(G = 1 V/V)
V
ISO
LOAD – mA
60
36
0
010123456789
56
40
32
24
48
44
28
52
16
20
12
4
8
0.33µF BYPASS CAPS
1.0µF BYPASS CAPS
3.3µF BYPASS CAPS
10µF BYPASS CAPS
V
ISO
RIPPLE – mV p-p
Figure 9.
±
V
ISO
Supply Ripple vs. Load
V
ISO
LOAD – ±mA
16.2
15.2
14.8
15510
16.0
15.4
15.8
15.6
15.0
V
ISO
±V
V
S
= ±15V dc
NOTE:
THE GAIN AND
OFFSET ERRORS
WILL INCREASE
WHEN THE
ISOLATED
POWER SUPPLY
LOAD EXCEEDS
±10mA
Figure 10.
±
V
ISO
Supply Voltage vs. Load
AD215
REV. 0
–7–
POWERING THE AD215
The AD215 is powered by a bipolar ±15 V dc power supply
connected as shown in Figure 11. External bypass capacitors
should be provided in bused applications. Note that a small
signal-related current (50 mA/V
OUT
) will flow out of the OUT
LO pin (Pin 37). Therefore, the OUT LO terminals should be
bused together and referenced at a single “Analog Star Ground”
to the ±15 V dc supply common as illustrated Figure 11.
AD215
N
AD215
1
OUT LO
N
N
TH
CHANNEL 1
ST
CHANNEL
ANALOG STAR GROUND
OUT LO
1
SIG COM
+V
IN
PWR RTN
–V
IN
+15V dc
COM
–15V dc
2.2µF
37
42
43
44
42
44
43
2.2µF
37
Figure 11. Typical Power Supply Connections
Power Supply Voltage Considerations
The rated performance of the AD215 remains unaffected for
power supply voltages in the ±14.5 V dc to ±16.5 V dc range.
Voltages below ±14.25 V dc may cause the AD215 to cease op-
erating properly.
Note: Power supply voltages greater than ±17.5 V dc may damage
the internal components and consequently should not be used.
USING THE AD215
Unity Gain Input Configuration
The basic unity gain configuration for input signals of up to
±10 V is shown in Figure 12.
R
IN
= 2k
V
SIGNAL
IN+
IN–
FB
IN COM
OUT HI
OUT LO
PWR
RTN
COM
TRIM
OUTPUT FILTER,
BUFFER AND
TRIM CIRCUITRY
1
3
4
2
38
36
37
43
AD215
Figure 12. Basic Unity Gain
Noninverting Configuration for Gain Greater Than Unity
Figure 13 shows how to achieve a gain greater than one while
continuing to preserve a very high input impedance. A recom-
mended PC board layout for multichannel applications is shown
in Figure 20b.
R
IN
= 2k
V
SIGNAL
IN+
IN–
FB
IN COM
OUT HI
OUT LO
PWR
RTN
COM
TRIM
OUTPUT
FILTER,
BUFFER
AND
TRIM
CIRCUITRY
1
3
4
2
38
36
37
43
AD215
C
F
47pF
R
F
R
G
Figure 13. Noninverting Input Configuration for
Gain > 1 V/V
In this circuit, the gain equation is as follows:
V
O
= (1 + R
F
/R
G
) × V
SIG
where:
V
O
= Output Voltage (V)
V
SIG
= Input Signal Voltage (V)
R
F
= Feedback Resistor Value ()
R
G
= Gain Resistor Value ()
The values for resistors R
F
and R
G
are subject to the following
constraints:
• The total impedance of the gain network should be less than
10 k.
• The current drawn in R
F
is less than 1 mA at ±10 V. Note that
for each mA drawn by the feedback resistor, the isolated
power supply drive capability decreases by 1 mA.
• Amplifier gain is set by the feedback (R
F
) and gain resistor
(R
G
).
It is recommended that R
F
is bypassed with a 47 pF capacitor as
shown.
Note: The 2 k input resistor (R
IN
) in series with the input
signal source and the IN+ terminal in Figures 12 and 13 is rec-
ommended to limit the current at the input terminals of the to
5.0 mA when the AD215 is not powered.
AD215
REV. 0
–8–
Compensating the Uncommitted Input Op Amp
The open-loop gain and phase versus frequency for the uncom-
mitted input op amp are given in Figure 14. These curves can
be used to determine appropriate values for the feedback resis-
tor (R
F
) and compensation capacitor (C
F
) to ensure frequency
stability when reactive or nonlinear components are used.
FREQUENCY – Hz
100k 100M1M
AVERAGE VOLTAGE GAIN – dB
10M
25
20
–25
15
10
5
0
–5
–10
–15
–20
PHASE
GAIN
Ø, EXCESS PHASE – Degrees
80
100
280
120
140
160
180
200
220
240
260
Figure 14. Open-Loop Gain and Frequency Response
Inverting, Summing or Current Input Configuration
Figure 14 shows how the AD215 can measure currents or sum
currents or voltages.
V
S1
IN+
IN–
FB
IN COM
OUT HI
OUT LO
PWR
RTN
COM
TRIM
OUTPUT
FILTER,
BUFFER
AND
TRIM
CIRCUITRY
1
3
4
2
38
36
37
43
AD215
C
F
47pF
R
F
R
S1
V
S2
R
S2
I
S
Figure 15. Noninverting Summing/Current Configuration
For this circuit, the output voltage equation is:
V
O
= –R
F
× (I
S
+ V
S1
/R
S1
+ V
S2
/R
S2
+ . . .)
where:
V = Output Voltage (V)
V
S1
= Input Voltage Signal 1 (V)
V
S2
= Input Voltage Signal 2 (V)
I
S
= Input Current Source (A)
R
F
= Feedback Resistor () (10 k, typ)
R
S1
= Input Signal 1 Source Resistance ()
R
S2
= Input Signal 2 Source Resistance ()
The circuit of Figure 15 can also be used when the input signal
is larger than the ±10 V input range of the isolator. For example,
in Figure 15, if only V
S1
, R
S1
and R
F
were connected as shown
with the solid lines, the input voltage span of V
S1
could accom-
modate up to ±50 V when R
F
= 10 k and R
S1
= 50 k.
GAIN AND OFFSET ADJUSTMENTS
General Comments
The AD215 features an output stage TRIM pin useful for zero-
ing the output offset voltage through use of user supplied circuitry.
When gain and offset adjustments are required, the actual com-
pensation circuit ultimately used depends on the following:
The input configuration mode of the isolation amplifier (non-
inverting or inverting).
The placement of any adjusting potentiometer (on the
isolator’s input or output side).
As a general rule:
Gain adjustments should be accomplished at the gain-setting
resistor network at the isolator’s input.
To ensure stability in the gain adjustment, potentiometers
should be located as close as possible to the isolator’s input
and its impedance should be kept low. Adjustment ranges
should also be kept to a minimum since their resolution and
stability is dependent upon the actual potentiometers used.
Output adjustments may be necessary where adjusting poten-
tiometers placed near the input would present a hazard to the
user due to the presence of high common-mode voltages dur-
ing the adjustment procedure.
It is recommended that input offset adjustments are made
prior to gain adjustments.
The AD215 should be allowed to warm up for approximately
10 minutes before gain or offset adjustments are made.
Input Gain Adjustments for Noninverting Mode
Figure 16 shows a suggested noninverting gain adjustment cir-
cuit. Note that the gain adjustment potentiometer R
P
is incorpo-
rated into the gain-setting resistor network.
R
IN
= 2k
V
SIGNAL
IN+
IN–
FB
IN COM
OUT HI
OUT LO
PWR
RTN
COM
TRIM
OUTPUT
FILTER,
BUFFER
AND
TRIM
CIRCUITRY
1
3
4
2
38
36
37
43
AD215
C
F
0.47pF
R
F
R
G
R
C
R
P
Figure 16. Gain Adjustment for Noninverting Configuration
For a ±1% trim range:
(R
P
1k), R
C
0.02 ×
R
G
× R
F
R
G
+ R
F

AD215AY

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Isolation Amplifiers 100KHz Bandwidth Iso AMP IC
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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