IR3621 & (PbF)
17
www.irf.com
From (20), R2 can be express as:
The power stage of current loop has a dominant pole (Fp)
at frequency expressed by:
F
p =
Where Req is the total resistance of the power stage
which includes the Rds(on) of the FET switches, the DCR
of inductor and shunt resistance (if it used).
Set the zero of compensator at 10 times the dominant
pole frequency Fp, the compensator capacitor, C2 can
be calculated as:
H(Fo) = gm×RS1×R2× =1 ---(20)
VIN
2π×Fo×L2×VOSC
R2 = ×
2π × F
O2 × L2 × VOSC
VIN
Layout Consideration
The layout is very important when designing high fre-
quency switching converters. Layout will affect noise
pickup and can cause a good design to perform with
less than expected results.
Start by placing the power components. Make all the
connections in the top layer with wide, copper filled ar-
eas. The inductor, output capacitor and the MOSFET
should be as close to each other as possible. This helps
to reduce the EMI radiated by the power traces due to
the high switching. Place input capacitor near to the
drain of the high-side MOSFET.
The layout of driver section should be designed for a low
resistance (a wide, short trace) and low inductance (a
wide trace with ground return path directly beneath it),
this directly affects the driver's performance.
To reduce the ESR, replace the one input capacitor with
two parallel ones. The feedback part of the system should
be kept away from the inductor and other noise sources
and must be placed close to the IC. In multilayer PCBs,
use one layer as power ground plane and have a sepa-
rate control circuit ground (analog ground), to which all
signals are referenced. The goal is to localize the high
current paths to a separate loops that does not interfere
with the more sensitive analog control function. These
two grounds must be connected together on the PC board
layout at a single point.
Select a zero crossover frequency for control loop (FO2)
1.25 times larger than zero crossover frequency for volt-
age loop (FO1):
1
gm × RS1
---(21)
Fo2 ≅ 1.25%xF01
Figure18- Case Temperature (TSSOP package) versus Switching Frequency at
Room Temperature
Test Condition: Vin=VcL=VcH1=VcH2=12V, Capacitors used as loads for output
drivers.
Switching Frequency vs. Case Temp
30
40
50
60
70
80
90
200 300 400 500 600 700
Freq (kHz)
Case temp (oC
100pF
1000pF
1800pF
3300pF
Req
2π×L2
Req=RDS(on)+RL+Rs
Fz = 10 x Fp
1
2πxR2xFz
C2 =
All design should be tested for stability to verify the cal-
culated values.
