MAX5168
Detailed Description
Digital Interface
The MAX5168 has three logic control inputs and five
address lines. The address lines are inputs to a demul-
tiplexer that selects one of the 32 outputs in a standard
addressing scheme (Table 1). The analog input is con-
nected to the addressed sample/hold when directed by
the control logic (Table 2).
The three logic control lines determine the state of the
addressed sample/hold. The normal circuit connection
for this device is to hardwire CONFIG and SELECT to
opposing logic voltages. When SELECT and CONFIG
are in opposite states (one high and the other low), the
five address lines select one of the sample/holds. Use
the S/H line to place the selected channel into sample
or hold mode. The other 31 channels will remain in hold
mode.
If an active-high sampling mode is desired, tie S/H and
CONFIG low. In this case, SELECT controls the
addressed channel with a high state putting that chan-
nel into sample mode.
The SELECT and CONFIG pins allow the design of a
virtual 64-channel device using two of the MAX5168s.
See the Applications Information section for more infor-
mation about 64-plus output addressing schemes.
Sample/Hold
The MAX5168 contains 32 buffered sample/hold circuits
with internal hold capacitors. Internal hold capacitors
minimize leakage current, dielectric absorption,
feedthrough, and required board space. The value of
the hold capacitor affects acquisition time and droop
rate. Smaller capacitance allows faster acquisition
times but increases the droop rate. Larger values
increase hold acquisition time. The hold capacitor used
in the MAX5168 provides fast 2.5µs (typ) acquisition
time while maintaining a relatively low 1mV/s (typ)
droop rate, making the sample/hold ideal for high-
speed sampling.
Sample Mode
When SELECT and CONFIG are in opposing logic states,
the S/H line controls the mode of operation. Sample mode
is entered when S/H is low. During sample mode, the
32-Channel Sample/Hold Amplifier
with a Single Multiplexed Input
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