15
LTC2421/LTC2422
24212f
interface with other devices. If CS is LOW during the con-
vert or sleep state, SDO will output EOC. If CS is LOW
during the conversion phase, the EOC bit appears HIGH on
the SDO pin. Once the conversion is complete, EOC goes
LOW. The device remains in the sleep state until the first
rising edge of SCK occurs while CS = 0. While in the sleep
state, the device is in a LOW power state if CS is HIGH.
Chip Select Input (CS)
The active LOW chip select, CS (Pin 7), is used to test the
conversion status and to enable the data output transfer as
described in the previous sections.
In addition, the CS signal can be used to trigger a new
conversion cycle before the entire serial data transfer has
been completed. The LTC2421/LTC2422 will abort any
serial data transfer in progress and start a new conversion
cycle anytime a LOW-to-HIGH transition is detected at the
CS pin after the converter has entered the data output state
(i.e., after the first rising edge of SCK occurs with CS = 0).
Finally, CS can be used to control the free-running modes
of operation, see Serial Interface Timing Modes section.
Grounding CS will force the ADC to continuously convert
at the maximum output rate selected by F
O
. Tying a ca-
pacitor to CS will reduce the output rate and power dissi-
pation by a factor proportional to the capacitor’s value,
see Figures 13 to 15.
SERIAL INTERFACE TIMING MODES
The LTC2421/LTC2422’s 3-wire interface is SPI and
MICROWIRE compatible. This interface offers several
flexible modes of operation. These include internal/exter-
nal serial clock, 2- or 3-wire I/O, single cycle conversion
and autostart. The following sections describe each of
these serial interface timing modes in detail. In all these
cases, the converter can use the internal oscillator (F
O
=
LOW or F
O
= HIGH) or an external oscillator connected to
the F
O
pin. Refer to Table 4 for a summary.
External Serial Clock, Single Cycle Operation
(SPI/MICROWIRE Compatible)
This timing mode uses an external serial clock to shift out
the conversion result and a CS signal to monitor and con-
trol the state of the conversion cycle, see Figure 6.
The serial clock mode is selected on the falling edge of CS.
To select the external serial clock mode, the serial clock pin
(SCK) must be LOW during each CS falling edge.
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
While CS is LOW, EOC is output to the SDO pin. EOC = 1
while a conversion is in progress and EOC = 0 if the device
is in the sleep state. Independent of CS, the device auto-
matically enters the sleep state once the conversion is
complete. While in the sleep state, power is reduced an
order of magnitude if CS is HIGH.
When the device is in the sleep state (EOC = 0), its
conversion result is held in an internal static shift register.
The device remains in the sleep state until the first rising
edge of SCK is seen while CS is LOW. Data is shifted out
the SDO pin on each falling edge of SCK. This enables
external circuitry to latch the output on the rising edge of
SCK. EOC can be latched on the first rising edge of SCK
and the last bit of the conversion result can be latched on
the 24th rising edge of SCK. On the 24th falling edge of
SCK, the device begins a new conversion. SDO goes HIGH
(EOC = 1) indicating a conversion is in progress.
Table 4. LTC2421/LTC2422 Interface Timing Modes
Conversion Data Connection
SCK Cycle Output and
Configuration Source Control Control Waveforms
External SCK, Single Cycle Conversion External CS and SCK CS and SCK Figures 6, 7
External SCK, 2-Wire I/O External SCK SCK Figure 8
Internal SCK, Single Cycle Conversion Internal CS ↓ CS ↓ Figures 9, 10
Internal SCK, 2-Wire I/O, Continuous Conversion Internal Continuous Internal Figure 11
Internal SCK, Autostart Conversion Internal C
EXT
Internal Figure 12
APPLICATIO S I FOR ATIO
WUUU
