74ABT652A_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 02 — 12 March 2010 9 of 19
NXP Semiconductors
74ABT652A
Octal transceiver/register; non-inverting; 3-state
10. Dynamic characteristics
[1] This data sheet limit may vary among suppliers.
Table 7. Dynamic characteristics
GND = 0 V; for test circuit, see Figure 12.
Symbol Parameter Conditions 25 °C; V
CC
= 5.0 V −40 °C to +85 °C;
V
CC
= 5.0 V ± 0.5 V
Unit
Min Typ Max Min Max
f
max
maximum
frequency
see Figure 6 125 300 - 125 - MHz
t
PLH
LOW to HIGH
propagation delay
CPAB to Bn or CPBA to An; see Figure 6 2.2 3.7 5.1 2.2 5.6 ns
An to Bn or Bn to An; see
Figure 7 1.5 3.0 4.3 1.5 4.8 ns
SAB to Bn or SBA to An; see
Figure 8 1.5 3.5 5.1 1.5 6.5 ns
t
PHL
HIGH to LOW
propagation delay
CPAB to Bn or CPBA to An; see Figure 6 1.7 4.3 5.1 1.7 5.6 ns
An to Bn or Bn to An; see
Figure 7 1.5 3.6 4.6 1.5 5.4 ns
SAB to Bn or SBA to An; see
Figure 8 1.5 4.2 5.2
[1]
1.5 5.9 ns
t
PZH
OFF-state to HIGH
propagation delay
OEBA to An; see Figure 10 2 3.2 4.6 2 5.8 ns
OEAB to Bn; see
Figure 10 2 3.5 6.1 2 6.5 ns
t
PZL
OFF-state to LOW
propagation delay
OEBA to An; see Figure 11 3 4.5 6.8 3 8.5 ns
OEAB to Bn; see
Figure 11 3 4.7 6.5 3 7.4 ns
t
PHZ
HIGH to OFF-state
propagation delay
OEBA to An; see Figure 10 1.5 3.9 4.7
[1]
1.5 5.3
[1]
ns
OEAB to Bn; see
Figure 10 1.5 3.8 4.6
[1]
1.5 5.5 ns
t
PLZ
LOW to OFF-state
propagation delay
OEBA to An; see Figure 11 1.5 2.9 3.8 1.5 4.1 ns
OEAB to Bn; see
Figure 11 1.5 3.0 4.4 1.5 5.1 ns
t
su(H)
set-up time HIGH An to CPAB, Bn to CPBA; see Figure 9 3.0 0.7 - 3.0 - ns
t
su(L)
set-up time LOW An to CPAB, Bn to CPBA; see Figure 9 3.0 0.7 - 3.0 - ns
t
h(H)
hold time HIGH An to CPAB, Bn to CPBA; see Figure 9 0.0 −0.5 - 0.0 - ns
t
h(L)
hold time LOW An to CPAB, Bn to CPBA; see Figure 9 0.0 −0.5 - 0.0 - ns
t
WH
pulse width HIGH CPAB, CPBA; see Figure 6 4.0 1.0 - 4.0 - ns
t
WL
pulse width LOW CPAB, CPBA; see Figure 6 4.0 1.0 - 4.0 - ns