NCV7703GEVB
http://onsemi.com
3
Typical connections to the evaluation board are shown in
Figure 4. The diagram illustrates half-bridge operation of a
motor, and the option for a high-side or low-side load. The
load connections are for illustration only and do not limit
other possible connections.
The connection of the battery or supply (to VB+) powers
the board. V
CC
for the NCV7703 may be powered by the
on−board regulator (powered from VB+) with the 5 V
jumper. Remove the 5 V jumper if powering from an
external source. LED D1 indicates when 5 V is present
(powered on-board or externally).
Notice the SO of the SPI controller connects to the SI of
the NCV7703GEVB, and the SO of the NCV7703GEVB
connects to the SI of the SPI controller.
The Enable jumper hard wires the Enable pin (EN) to be
on. The Enable function may also be provided by the SPI
Controller. Disconnect the Enable jumper when providing
the signal externally.
Refer to the data sheet for SPI interface functionality.
Figure 4. Typical NCV7703 Power Connections
SPI Communication
Standard 16-bit communication has been implemented
for the communication of this IC to turn drivers on and off,
and to report faults. The LSB (Least Significant Bit) is
clocked in first.
Communication is implemented as follows:
1. CSB goes low to allow serial data transfer.
2. A 16 bit word is clocked (SCLK) into the SI
(Serial Input) pin.
3. CSB goes high to transfer the clocked in
information to the data registers.
Note SO is tristate when CSB is high.
4. The SI data will be accepted when a valid SPI
frame is detected. A valid SPI frame consists of
the above conditions and a complete set of
multiples of 16 bit words.
