NTB65N02R, NTP65N02R
http://onsemi.com
4
0
400
800
1200
1600
2000
10 5 0 5 10 15 20
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE
(V)
Figure 7. Capacitance Variation
C, CAPACITANCE (pF)
T
J
= 25°C
V
GS
= 0 V
C
iss
C
oss
C
rss
C
iss
V
DS
= 0 V
C
rss
V
GS
V
DS
0
1
2
3
4
5
0461012
Q
g
, TOTAL GATE CHARGE (nC)
Figure 8. Gate−to−Source and Drain−to−Source
Voltage versus Total Charge
Q
GS
Q
GD
V
GS
I
D
= 30 A
T
J
= 25°C
1
10
100
1000
1 10 100
R
G
, GATE RESISTANCE ()
Figure 9. Resistive Switching Time Variation
versus Gate Resistance
t, TIME (ns)
V
DS
= 10 V
I
D
= 30 A
V
GS
= 10 V
1
10
1000
0.1 1 10 100
R
DS(ON)
LIMIT
THERMAL LIMIT
PACKAGE LIMIT
10 s
100 s
1 ms
10 ms
dc
V
GS
= 20 V
SINGLE PULSE
T
C
= 25°C
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
I
D
, DRAIN CURRENT (A)
0
10
20
30
40
50
60
0 0.2 0.4 0.6 0.8 1
Figure 10. Diode Forward Voltage versus
Current
V
SD
, SOURCE−TO−DRAIN VOLTAGE (V)
Figure 11. Maximum Rated Forward Biased Safe Operating Area
I
S
, SOURCE CURRENT (A)
T
J
= 25°C
T
J
= 150°C
t
r
t
d(off)
t
f
t
d(on)
V
GS
, GATE−TO−SOURCE VOLTAGE (V)
100
28
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
0
2
4
6
8
10
V
DS
Q
T
