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70V09L15PFG

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
IDT70V09L
High-Speed 128K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
4
Truth Table III – Semaphore Read/Write Control
(1)
Truth Table I – Chip Enable
(1,2)
NOTES:
1. Chip Enable references are shown above with the actual CE
0 and CE1 levels; CE is a reference only.
2. 'H' = V
IH and 'L' = VIL.
3. CMOS standby requires 'X' to be either
< 0.2V or >VCC-0.2V.
Truth Table II – Non-Contention Read/Write Control
NOTES:
1. A
0L — A16L ≠ A0R — A16R
2. Refer to Truth Table I - Chip Enable.
NOTES:
1. There are eight semaphore flags written to I/O
0 and read from all the I/Os (I/O0-I/O7). These eight semaphore flags are addressed by A0-A2.
2. Refer toTruth Table I -
Chip Enable .
CE CE
0
CE
1
Mode
L
V
IL
V
IH
Port Selected (TTL Active)
<
0.2V >V
CC
-0.2V Port Selected (CMOS Active)
H
V
IH
X Port Deselected (TTL Inactive)
XV
IL
Port Deselected (TTL Inactive)
>
V
CC
-0.2V X
(3)
Port Deselected (CMOS Inactive)
X
(3 )
<0.2V Port Deselected (CMOS Inactive)
4852 tbl 06
Inputs
(1 )
Outputs
Mode
CE
(2 )
R/W
OE SE M
I/O
0-7
H X X H High-Z Deselected: Power-Down
LLXHDATA
IN
Write to Memory
LHLHDATA
OUT
Read Memory
X X H X High-Z Outputs Disabled
4852 tbl 07
Inputs Outputs
Mode
CE
(2 )
R/W
OE SEM
I/O
0-7
HHLLDATA
OUT
Read Semaphore Flag Data Out
H
↑
XLDATA
IN
Write I/O
0
into Semaphore Flag
LXXL
______
Not Allowed
4852 tbl 08
5
IDT70V09L
High-Speed 128K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range
(5)
(VCC = 3.3V ± 0.3V)
NOTES:
1. V
CC = 3.3V, TA = +25°C, and are not production tested. ICCDC = 90mA (Typ.)
2. At f = f
MAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions" of input levels of GND
to 3V.
3. f = 0 means no address or control lines change.
4. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
5. Refer to Truth Table I - Chip Enable.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range
(VCC = 3.3V ± 0.3V)
NOTES:
1. At Vcc
< 2.0V, input leakages are undefined.
2. Refer to Truth Table I -
Chip Enable.
Symbol Parameter Test Conditions
70V09L
UnitMin. Max.
|I
LI
| Input Leakage Current
(1)
V
CC
= 3.6V, V
IN
= 0V to V
CC
___
5µA
|I
LO
| Output Leakage Current
CE
(2 )
= V
IH
, V
OUT
= 0V to V
CC
___
5µA
V
OL
Output Low Voltage I
OL
= +4mA
___
0.4 V
V
OH
Output High Voltage I
OH
= -4mA 2.4
___
V
4852 tbl 09
70V09L15
Com'l Only
70V09L20
Com'l
& Ind
Symbol Parameter Test Condition Version Typ.
(1)
Max. Typ.
(1)
Max.
Unit
I
CC
Dynamic Operating
Current
(Both Ports Active)
CE = V
IL
, Outputs Disabled
SEM = V
IH
f = f
MAX
(2 )
COM'L L 145 235 135 205
mA
IND L
____
____
135 220
I
SB1
Standby Current
(Both Ports - TTL Level
Inputs)
CE
L
= CE
R
= V
IH
SEM
R
= SEM
L
= V
IH
f = f
MAX
(2 )
COM'L L 40 70 35 55
mA
IND L
____
____
35 65
I
SB2
Standby Current
(One Port - TTL Level
Inputs)
CE
"A"
= V
IL
and CE
"B"
= V
IH
(4 )
Active Port Outputs Disabled,
f=f
MAX
(2 )
,
SEM
R
= SEM
L
= V
IH
COM'L L 100 155 90 140
mA
IND L
____
____
90 150
I
SB3
Full Standby Current
(Both Ports - All CMOS
Level Inputs)
Both Ports CE
L
and CE
R
> V
CC
- 0.2V,
V
IN
> V
CC
- 0.2V or V
IN
< 0.2V, f = 0
(3)
SEM
R
= SEM
L
> V
CC
- 0.2V
COM'L L 0.2 3.0 0.2 3.0
mA
IND L
____
____
0.2 3.0
I
SB4
Full Standby Current
(One Port - All CMOS
Level Inputs)
CE
"A"
< 0.2V and CE
"B"
> V
CC
- 0.2V
(4 )
,
SEM
R
= SEM
L
> V
CC
- 0.2V,
V
IN
> V
CC
- 0.2V or V
IN
< 0.2V,
Active Port Outputs Disabled, f = f
MAX
(2)
COM'L L 95 150 90 135
mA
IND L
____ ____
90 145
4852 tbl 10
IDT70V09L
High-Speed 128K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
6
Timing of Power-Up Power-Down
Waveform of Read Cycles
(5)
NOTES:
1. Timing depends on which signal is asserted last, OE or CE.
2. Timing depends on which signal is de-asserted first CE or OE.
3. t
BDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY has no
relation to valid output data.
4. Start of valid data depends on which timing becomes effective last t
AOE, tACE, tAA or tBDD.
5. SEM = V
IH.
6. Refer to Truth Table I - Chip Enable.
CE
(6)
4852 drw 06
t
PU
I
CC
I
SB
t
PD
50% 50%
.
t
RC
R/W
CE
(6)
ADDR
t
AA
OE
4852 drw 05
(4)
t
ACE
(4)
t
AOE
(4)
(1)
t
LZ
t
OH
(2)
t
HZ
(3,4)
t
BDD
DATA
OUT
BUSY
OUT
VALID DATA
(4)
AC Test Conditions
Figure 1. AC Output Load
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
3ns Max.
1.5V
1.5V
Figures 1 and 2
4852 tbl 11
4852 drw 04
590Ω
30pF
435Ω
3.3V
DATA
OUT
BUSY
INT
590Ω
5pF*
435Ω
3.3V
DATA
OUT
4852 drw 03
Figure 2. Output Test Load
(for t
LZ, tHZ, tWZ, tOW)
* Including scope and jig.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

70V09L15PFG

Mfr. #:
Buy 70V09L15PFG
Manufacturer:
IDT
Description:
SRAM Low Power Dual-Port RAM IC
Lifecycle:
New from this manufacturer.
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