HMCAD1041-40 Datasheet HMCAD1041-40 | P10-P12

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A / D CONVERTERS - SMT

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HMCAD1041-40

v01.0411

SINGLE 10-BIT 20/40 MSPS A/D CONVERTER

Figure 6: Transformer coupled input

Figure 7 shows AC-coupling using capacitors. Resis-

tors from the CM_EXT output, RCM, should be used

to bias the differential input signals to the correct volt-

age. The series capacitor, CI, form the high-pass pole

with these resistors, and the values must therefore be

determined based on the requirement to the high-pass

cut-off frequency.

Figure 7: AC coupled input

Note that startup time from Sleep Mode and Power

Down Mode will be affected by this lter as the time

required to charge the series capacitors is dependent

on the lter cut-off frequency.

If the input signal has a long traveling distance, and the

kick-backs from the ADC not are effectively terminated

at the signal source, the input network of gure 8 can

be used. The conguration in gure 8 is designed to

attenuate the kickback from the ADC and to provide

an input impedance that looks as resistive as possible

for frequencies below Nyquist. Values of the series

inductor will however depend on board design and

conversion rate. In some instances a shunt capaci-

tor in parallel with the termination resistor (e.g. 33pF)

may improve ADC performance further. This capacitor

attenuate the ADC kick-back even more, and minimize

the kicks traveling towards the source. However, the

impedance match seen into the transformer becomes

worse.

Figure 8: Alternative input network

Clock Input and Jitter Considerations

Typically high-speed ADCs use both clock edges to

generate internal timing signals. In the HMCAD1041-

40 only the rising edge of the clock is used. Hence,

input clock duty cycles between 20% and 80% are

acceptable.

The input clock can be supplied in a variety of formats.

The clock pins are AC-coupled internally. Hence a

wide common mode voltage range is accepted. Differ-

ential clock sources as LVDS, LVPECL or differential

sine wave can be connected directly to the input pins.

For CMOS inputs, the CKN pin should be connected

to ground, and the CMOS clock signal should be con-

nected to CKP. For differential sine wave clock, the

input amplitude must be at least ± 800 mVpp.

The quality of the input clock is extremely important

for high-speed, high-resolution ADCs. The contribu-

tion to SNR from clock jitter with a full scale signal at a

given frequency is shown in equation 1,

SNR

jitter

= 20 · log (2 · π · ƒ

· є

) (1)

where fIN is the signal frequency, and

is the total

rms jitter measured in seconds. The rms jitter is the

total of all jitter sources including the clock generation

circuitry, clock distribution and internal ADC circuitry.

For applications where jitter may limit the obtainable

performance, it is of utmost importance to limit the

clock jitter. This can be obtained by using precise and

stable clock references (e.g. crystal oscillators with

good jitter specications) and make sure the clock dis-

tribution is well controlled. It might be advantageous

to use analog power and ground planes to ensure

low noise on the supplies to all circuitry in the clock

distribution. It is of utmost importance to avoid cross-

talk between the ADC output bits and the clock and

between the analog input signal and the clock since

such crosstalk often results in harmonic distortion.

The jitter performance is improved with reduced rise

and fall times of the input clock. Hence, optimum jitter

performance is obtained with LVDS or LVPECL clock

with fast edges. CMOS and sine wave clock inputs will

result in slightly degraded jitter performance.

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

For price, delivery, and to place orders: Analog Devices, Inc.,

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106

Phone: 781-329-4700 • Order online at www.analog.com

Application Support: Phone: 1-800-ANALOG-D

For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824

978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com

Application Support: apps@hittite.com

A / D CONVERTERS - SMT

0 - 11

HMCAD1041-40

v01.0411

SINGLE 10-BIT 20/40 MSPS A/D CONVERTER

If the clock is generated by other circuitry, it should

be re-timed with a low jitter master clock as the last

operation before it is applied to the ADC clock input.

Digital Outputs

Digital output data are presented on parallel CMOS

form. The voltage on the OVDD pin set the levels of the

CMOS outputs. The output drivers are dimensioned to

drive a wide range of loads for OVDD above 2.25V,

but it is recommended to minimize the load to ensure

as low transient switching currents and resulting noise

as possible. In applications with a large fanout or large

capacitive loads, it is recommended to add external

buffers located close to the ADC chip.

The timing is described in the Timing Diagram section.

Note that the load or equivalent delay on CK_EXT

always should be lower than the load on data outputs

to ensure sufficient timing margins.

The digital outputs can be set in tristate mode by set-

ting the OE_N signal high.

The HMCAD1041-40 employs digital offset correc-

tion. This means that the output code will be 4096 with

shorted inputs. However, small mismatches in para-

sitics at the input can cause this to alter slightly. The

offset correction also results in possible loss of codes

at the edges of the full scale range. With no offset

correction, the ADC would clip in one end before the

other, in practice resulting in code loss at the oppo-

site end. With the output being centered digitally, the

output will clip, and the out of range ags will be set,

before max code is reached. When out of range ags

are set, the code is forced to all ones for overrange

and all zeros for underrange.

Data Format Selection

The output data are presented on offset binary form

when DFRMT is low (connect to OVSS). Setting

DFRMT high (connect to OVDD) results in 2’s comple-

ment output format. Details are shown in table 3.

Table 3: Data Format Description for 2Vpp Full Scale Range

Differential Input Voltage (IP - IN)

Output Data: D_9 : D_0

(DFRMT = 0, Offset Binary)

Output Data: D_9 : D_0

(DFRMT = 1, 2’s Complement)

1.0 V 11 1111 1111 01 1111 1111

+0.24mV 10 0000 0000 00 0000 0000

-0.24mV 01 1111 1111 11 1111 1111

-1.0V 00 0000 0000 10 0000 0000

Reference Voltages

The reference voltages are internally generated and

buffered based on a bandgap voltage reference. No

external decoupling is necessary, and the reference

voltages are not available externally. This simplies

usage of the ADC since two extremely sensitive pins,

otherwise needed, are removed from the interface.

Operational Modes

The operational modes are controlled with the PD_N

and SLP_N pins. If PD_N is set low, all other control

pins are overridden and the chip is set in Power Down

mode. In this mode all circuitry is completely turned off

and the internal clock is disabled. Hence, only leak-

age current contributes to the Power Down Dissipa-

tion. The startup time from this mode is longer than

for Sleep Mode as all references need to settle to their

nal values before normal operation can resume.

The SLP_N signal can be used to set the full chip in

Sleep Mode. In this mode internal clocking is disabled,

but some low bandwidth circuitry is kept on to allow for

a short startup time. However, Sleep Mode represents

a signicant reduction in supply current, and it can be

used to save power even for short idle periods.

The input clock should be kept running in all idle

modes. However, even lower power dissipation is pos-

sible in Power Down mode if the input clock is stopped.

In this case it is important to start the input clock prior

to enabling active mode.

Startup Initialization

The HMCAD1041-40 must be reset prior to normal

operation. This is required every time the power

supply voltage has been switched off. A reset is per-

formed by applying Power Down mode. Wait until a

stable supply voltage has been reached, and pull the

PD_N pin for the duration of at least one clock cycle.

The input clock must be running continuously during

this Power Down period and until active operation

is reached. Alternatively the PD pin can be kept low

during power-up, and then be set high when the power

supply voltage is stable.

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

For price, delivery, and to place orders: Analog Devices, Inc.,

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106

Phone: 781-329-4700 • Order online at www.analog.com

Application Support: Phone: 1-800-ANALOG-D

For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824

978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com

Application Support: apps@hittite.com

A / D CONVERTERS - SMT

0 - 12

HMCAD1041-40

v01.0411

SINGLE 10-BIT 20/40 MSPS A/D CONVERTER

Outline Drawing

Table 4: 6x6 mm QFN (40 Pin LP6H) Dimensions

Symbol

Millimeter Inch

Min Typ Max Min Typ Max

A 0.9 0.035

A1 0 0.01 0.05 0 0.000 0.002

A2 0.65 0.7 0.026 0.028

A3 0.2 REF 0.008 REF

b 0.2 0.25 0.32 0.008 0.01 0.013

D 6.00 bsc 0.236 bsc

D1 5.75 bsc 0.226 bsc

D2 3.95 4.1 4.25 0.156 0.162 0.167

L 0.3 0.4 0.5 0.012 0.016 0.02

e 0.50 bsc 0.020 bsc

Θ1 0° 12° 0° 12°

F 0.2 0.008

G 0.24 0.42 0.6 0.010 0.017 0.024

Package Information

Part Number Package Body Material Lead Finish MSL

[1]

Package Marking

[2]

HMCAD1041-40 RoHS-compliant Low Stress Injection Molded Plastic 100% matte Sn Level 2A

ASD0401

XXXX

[1] MSL, Peak Temp: The moisture sensitivity level rating classied according to the JEDEC industry standard and to peak solder temperature.

[2] Proprietary marking XXXX, 4-Digit lot number XXXX

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

For price, delivery, and to place orders: Analog Devices, Inc.,

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106

Phone: 781-329-4700 • Order online at www.analog.com

Application Support: Phone: 1-800-ANALOG-D

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HMCAD1041-40

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Manufacturer:

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