DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs
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ORDERING INFORMATION
PART TEMP RANGE PIN-PACKAGE
VOLTAGE
(V)
TOP MARK**
DS1743-85 0°C to +70°C 28 EDIP Module 5 DS1743-85
DS1743-100 0°C to +70°C 28 EDIP Module 5 DS1743-100
DS1743-100 IND -40°C to +85°C 28 EDIP Module 5 DS1743-100-IND
DS1743P-85 0°C to +70°C 34 PowerCap* 5 DS1743P-85
DS1743P-100 0°C to +70°C 34 PowerCap* 5 DS1743P-100
DS1743P-100IND -40°C to +85°C 34 PowerCap* 5 DS1743P-100 IND
DS1743W-120 0°C to +70°C 28 EDIP Module 3.3 DS1743W-120
DS1743W-120 IND -40°C to +85°C 28 EDIP Module 3.3 DS1743W-120 IND
DS1743W-150 0°C to +70°C 28 EDIP Module 3.3 DS1743W-150
DS1743W-150 IND -40°C to +85°C 28 EDIP Module 3.3 DS1743W-150 IND
DS1743WP-120 0°C to +70°C 34 PowerCap* 3.3 DS1743WP-120
DS1743WP-120 IND -40°C to +85°C 34 PowerCap* 3.3 DS1743WP-120 IND
DS1743-85+ 0°C to +70°C 28 EDIP Module 5 DS1743-85
DS1743-100+ 0°C to +70°C 28 EDIP Module 5 DS1743-100
DS1743-100 IND+ -40°C to +85°C 28 EDIP Module 5 DS1743-100-IND
DS1743P-85+ 0°C to +70°C 34 PowerCap* 5 DS1743P-85
DS1743P-100+ 0°C to +70°C 34 PowerCap* 5 DS1743P-100
DS1743P-100IND+ -40°C to +85°C 34 PowerCap* 5 DS1743P-100 IND
DS1743W-120+ 0°C to +70°C 28 EDIP Module 3.3 DS1743W-120
DS1743W-120 IND+ -40°C to +85°C 28 EDIP Module 3.3 DS1743W-120 IND
DS1743W-150+ 0°C to +70°C 28 EDIP Module 3.3 DS1743W-150
DS1743W-150 IND+ -40°C to +85°C 28 EDIP Module 3.3 DS1743W-150 IND
DS1743WP-120+ 0°C to +70°C 34 PowerCap* 3.3 DS1743WP-120
DS1743WP-120 IND+ -40°C to +85°C 34 PowerCap* 3.3 DS1743WP-120 IND
DS9034PCX
0°C to +70°C PowerCap — DS9034PC
DS9034I-PCX -40°C to +85°C PowerCap IND — DS9034PCI
DS9034PCX+ 0°C to +70°C PowerCap — DS9034PC
DS9034I-PCX+ -40°C to +85°C PowerCap IND — DS9034PCI
+Denotes a lead(Pb)-free/RoHS-compliant package.
*DS9034PCX required (must be ordered separately).
**A ‘+’ indicates lead(Pb)-free. The top mark will include a ‘+’ symbol on lead(Pb)-free devices.
DESCRIPTION
The DS1743 is a full-function, year-2000-compliant (Y2KC), real-time clock/calendar (RTC) and 8k x 8
nonvolatile static RAM. User access to all registers within the DS1743 is accomplished with a bytewide
interface as shown in Figure 1. The RTC information and control bits reside in the eight uppermost RAM
locations. The RTC registers contain century, year, month, date, day, hours, minutes, and seconds data in
24-hour binary-coded decimal (BCD) format. Corrections for the day of the month and leap year are made
automatically. The RTC clock registers are double buffered to avoid access of incorrect data that can occur
during clock update cycles. The double-buffered system also prevents time loss as the timekeeping
countdown continues unabated by access to time register data. The DS1743 also contains its own power-
fail circuitry, which deselects the device when the V
CC
supply is in an out-of-tolerance condition. When
V
CC
is above V
PF
, the device is fully accessible. When V
CC
is below V
PF
, the internal CE signal is forced
high, preventing any access. When V
CC
rises above V
PF
, access remains inhibited for T
REC
, allowing time
for the system to stabilize. These features prevent loss of data from unpredictable system operation brought
on by low V
CC
as errant access and update cycles are avoided.
