DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs
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AC TEST CONDITIONS
Output Load: 50 pF + 1TTL Gate
Input Pulse Levels: 0 to 3.0V
Timing Measurement Reference Levels:
Input: 1.5V
Output: 1.5V
Input Pulse Rise and Fall Times: 5ns
NOTES:
1) Voltages are referenced to ground.
2) Typical values are at +25C and nominal supplies.
3) Outputs are open.
4) Battery switchover occurs at the lower of either the battery terminal voltage or V
PF
.
5) The CE2 control signal functions the same as the CE signal except that the logic levels for active and
inactive levels are opposite. If CE2 is used to terminate a write, the CE2 data hold time (t
DH
) applies.
6) Data-retention time is at +25C.
7) Each DS1743 has a built-in switch that disconnects the lithium source until V
CC
is first applied by the
user. The expected tDR is defined for DIP modules as a cumulative time in the absence of V
CC
starting
from the time power is first applied by the user.
8) RTC Encapsulated DIP Modules (EDIP) can be successfully processed through conventional wave-
soldering techniques as long as temperatures as long as temperature exposure to the lithium energy
source contained within does not exceed +85C. Post-solder cleaning with water-washing techniques is
acceptable, provided that ultrasonic vibration is not used. See the PowerCap package drawing for
details regarding the PowerCap package.
