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MAX17500AEUB+T

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18
MAX17499/MAX17500
For the MAX17500, the voltage at IN is normally derived
from a tertiary winding of the transformer. However, at
startup there is no energy being delivered through the
transformer; hence, a special bootstrap sequence is
required. Figure 2 shows the voltages at V
IN
and V
CC
during startup. Initially, both V
IN
and V
CC
are 0V. After
the line voltage is applied, C1 charges through the
startup resistor, R1, to an intermediate voltage. At this
point, the internal regulator begins charging C2 (see
Figure 1). Only 50μA of the current supplied through R1
is used by the MAX17500; the remaining input current
charges C1 and C2. The charging of C2 stops when
the V
CC
voltage reaches approximately 9.5V, while the
voltage across C1 continues rising until it reaches the
wake-up level of 21.6V. Once V
IN
exceeds the boot-
strap UVLO threshold, NDRV begins switching the
MOSFET and transfers energy to the secondary and
tertiary outputs. If the voltage on the tertiary output
builds to higher than 9.74V (the bootstrap UVLO lower
threshold), then startup has been accomplished and
sustained operation commences. If V
IN
drops below
9.74V before startup is complete, the device goes back
to low-current UVLO. In this case, increase the value of
C1 to store enough energy to allow for the voltage at
the tertiary winding to build up.
UVLO Flag (UFLG)
The devices have an open-drain undervoltage flag out-
put (UFLG). When used with an optocoupler, the UFLG
output can serve to sequence a secondary-side con-
troller. An internal 210μs delay occurs the instant the
voltage on UVLO/EN drops below 1.17V until NDRV
stops switching. This allows for the UFLG output to
change state before the devices shut down (Figure 3).
When the voltage at the UVLO/EN is above the thresh-
old, UFLG is high impedance. When UVLO/EN is below
the threshold, UFLG goes low. UFLG is not affected by
bootstrap UVLO (MAX17500).
Current-Mode PWM Controllers with
Programmable Switching Frequency
10 ______________________________________________________________________________________
MAX17499/MAX17500 fig02
100ms/div
V
CC
2V/div
V
IN
5V/div
0V
Figure 2. V
IN
and V
CC
During Startup When Using the
MAX17500 in Bootstrapped Mode (Figure 1)
V
UVLO/EN
LOW
LOW
HIGH-Z
V
UFLG
V
NDRV
SHUTDOWN
SHUTDOWN
t
EXTR
3ms
1.23V
(±1%)
1.17V (typ)
t
EXTF
210μs
0.6μs
3μs
NDRV SWITCHING
Figure 3. UVLO/EN and UFLG Operation Timing
Soft-Start
The devices’ soft-start feature allows the output voltage
to ramp up in a controlled manner, eliminating voltage
overshoot. The devices’ reference generator that is
internally connected to the error amplifier soft-starts to
achieve superior control of the output voltage under
heavy- and light-load conditions. Soft-start begins after
UVLO is deasserted (V
IN
is above 21.6V for the
MAX17500, V
IN
is above 9.5V for the MAX17499, and
the voltage on UVLO/EN is above 1.23V). The voltage
applied to the noninverting node of the amplifier ramps
from 0 to 1.23V in 1984 NDRV switching cycles. Use the
following formula to calculate the soft-start time (t
SS
):
where f
NDRV
is the switching frequency at the NDRV
output. Figure 4 shows the soft-start regulated output of
a power supply using the MAX17500 during startup.
n-Channel MOSFET Switch Driver
The NDRV output drives an external n-channel MOSFET.
The internal regulator output (V
CC
), set to approximately
9V, drives NDRV. For the universal input voltage range,
the MOSFET used must withstand the DC level of the
high-line input voltage plus the reflected voltage at the
primary of the transformer. Most applications that use the
discontinuous flyback topology require a MOSFET rated
at 600V. NDRV can source/sink in excess of 650mA/
1000mA peak current; therefore, select a MOSFET that
mA yields acceptable conduction and switching losses.
Oscillator/Switching Frequency
Use an external resistor at RT to program the devices’
internal oscillator frequency between 50kHz and 2.5MHz.
The MAX17499A/MAX17500A output switching frequen-
cy is one-half the programmed oscillator frequency with a
50% duty cycle. The MAX17499B/MAX17500B output
switching frequency is one-quarter of the programmed
oscillator frequency with a 75% duty cycle.
The MAX17499A/MAX17500A and MAX17499B/
MAX17500B have programmable output switching fre-
quencies from 25kHz to 625kHz and 12.5kHz to
625kHz, respectively. Use the following formulas to
determine the appropriate value of resistor R12 (see
Figure 1) needed to generate the desired output
switching frequency (f
SW
) at the NDRV output:
where R12 is the resistor connected from RT to GND
(see Figure 1).
Connect an RC network in parallel with R12 as shown in
Figure 1. The RC network should consist of a 100nF
capacitor, C6, (for stability) in series with resistor R15,
which serves to further minimize jitter. Use the following
formula to determine the value of R15:
For example, if R12 is 4kΩ, R15 becomes 707Ω.
Internal Error Amplifier
The devices include an internal error amplifier to regu-
late the output voltage in the case of a nonisolated
power supply (see Figure 1). For the circuit in Figure 1,
calculate the output voltage using the following equation:
where V
REF
= 1.23V. The amplifier’s noninverting input
is internally connected to a digital soft-start circuit that
gradually increases the reference voltage during start-
up applied to this input. This forces the output voltage
to come up in an orderly and well-defined manner
under all load conditions.
The error amplifier may also be used to regulate the ter-
tiary winding output, which implements a primary-side-
regulated, isolated power supply (see Figure 6). For the
V
R
R
V
OUT REF
=+
⎛
⎝
⎜
⎞
⎠
⎟
1
13
14
RR15 88 9 12
1
4
.=×
()
R
f
for the MAX A MAX A
R
SW
12
10
2
17499 17500
12
10
= .
==
10
4
17499 17500
10
f
for the MAX B MAX B
SW
.
t
f
SS
NDRV
=
1984
MAX17499/MAX17500
Current-Mode PWM Controllers with
Programmable Switching Frequency
______________________________________________________________________________________ 11
MAX17499/MAX17500 fig04
2ms/div
V
OUT
2V/div
100mA LOAD ON/V
OUT1
100mA LOAD ON/V
OUT2
Figure 4. Primary-Side Output Voltage Soft-Start During Initial
Startup for the Circuit in Figure 6
MAX17499/MAX17500
circuit in Figure 6, calculate the output voltage using
the following equation:
where N
S
is the number of secondary winding turns, N
T
is the number of tertiary winding turns, and both V
D6
and V
D2
are the diode drops at the respective outputs.
Current Limit
The current-sense resistor (R4 in Figure 1), connected
between the source of the MOSFET and ground, sets the
current limit. The current-limit comparator has a voltage
trip level (V
CS
) of 1V. Use the following equation to cal-
culate the value of R4:
where I
PRI
is the peak current in the primary side of the
transformer, which also flows through the MOSFET.
When the voltage produced by this current (through the
current-sense resistor) exceeds the current-limit com-
parator threshold, the MOSFET driver (NDRV) termi-
nates the current on-cycle within 60ns (typ). Use a
small RC network to filter out the leading-edge spikes
on the sensed waveform when needed. Set the corner
frequency between 2MHz and 10MHz.
Applications Information
Startup Time Considerations for Power
Supplies Using the MAX17500
The bypass capacitor at IN, C1, supplies current imme-
diately after the MAX17500 wakes up (see Figure 1).
The size of C1 and the connection configuration of the
tertiary winding determine the number of cycles avail-
able for startup. Large values of C1 increase the start-
up time but also supply gate charge for more cycles
during initial startup. If the value of C1 is too small, V
IN
drops below 9.74V because NDRV does not have
enough time to switch and build up sufficient voltage
across the tertiary output, which powers the device.
The device goes back into UVLO and does not start.
Use a low-leakage capacitor for C1 and C2.
Typically, offline power supplies keep startup times to
less than 500ms even in low-line conditions (85V AC
input for universal offline or 36V DC for telecom appli-
cations). Size the startup resistor, R1, to supply both
the maximum startup bias of the device (90μA) and the
charging current for C1 and C2. The bypass capacitor,
C2, must charge to 9.5V and C1 to 24V, all within the
desired time period of 500ms. Because of the internal
soft-start time of the MAX17500 (approximately 5.6ms
when f
SW
= 350kHz), C1 must store enough charge to
deliver current to the device for at least this much time.
To calculate the approximate amount of capacitance
required, use the following formula:
where I
IN
is the MAX17500’s internal supply current
(2mA) after startup, Q
GTOT
is the total gate charge for
Q1, f
SW
is the MAX17500’s switching frequency
(350kHz), V
HYST
is the bootstrap UVLO hysteresis
(approximately 12V), and t
SS
is the internal soft-start
time (5.6ms).
Example: I
G
= (8nC) (350kHz) ≅ 2.8mA
Choose a 2.2μF standard value (assuming 350kHz
switching frequency).
Assuming C1 > C2, calculate the value of R1 as follows:
where V
IN(MIN)
is the minimum input supply voltage for
the application (36V for telecom), V
SUVR
is the boot-
strap UVLO wake-up level (23.6V max), and I
START
is
the IN supply current at startup (90μA max).
For example:
Choose a 61.9kΩ standard value.
()(.)
()
.
()(
I
VμF
ms
mA
R
V
C1
24 2 2
500
0 105
1
36 2
==
≅
−
44
0 105 90
61 5
V
mA μA
k
)
(. ) ( )
.
+
=Ω
I
VC
ms
R
VV
II
C
SUVR
IN MIN SUVR
CS
1
1
1
500
1
=
≅
−
+
()
()
TTART
C
mA mA ms
V
μF1
22856
12
224=
+
=
(.)(.)
.
IQ f
C
IIt
V
GGTOTSW
IN G SS
HYST
=
=
+
1
()()
R
V
I
CS
PRI
4 =
V
N
N
R
R
VVV
OUT
S
T
REF D D
=+
⎛
⎝
⎜
⎞
⎠
⎟
+
⎡
⎣
⎢
⎤
⎦
⎥
−1
1
2
62
Current-Mode PWM Controllers with
Programmable Switching Frequency
12 ______________________________________________________________________________________
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18

MAX17500AEUB+T

Mfr. #:
Buy MAX17500AEUB+T
Manufacturer:
Maxim Integrated
Description:
Switching Controllers w/Prog Switch Frequency
Lifecycle:
New from this manufacturer.
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