Power supplies designed with the MAX17500 use a
high-value startup resistor, R1, that charges a reservoir
capacitor, C1 (see Figure 1). During this initial period,
while the voltage is less than the internal bootstrap
UVLO threshold, the device typically consumes only
50μA of quiescent current. This low startup current and
the large bootstrap UVLO hysteresis help to minimize
the power dissipation across R1 even at the high end of
the universal AC input voltage (265V AC).
The devices include a cycle-by-cycle current limit that
turns off the gate drive to the external MOSFET when-
ever the internally set threshold of 1V is exceeded.
When using the MAX17500 in bootstrapped mode, if
the power-supply output is shorted, the tertiary winding
voltage drops below the internally set threshold caus-
ing the UVLO to turn off the gate drive to the external
power MOSFET. This reinitiates a startup sequence
with soft-start.
Current-Mode Control Loop
The advantages of current-mode control over voltage-
mode control are twofold. First, there is the feed-for-
ward characteristic brought on by the controller’s
ability to adjust for variations in the input voltage on a
cycle-by-cycle basis. Secondly, the stability require-
ments of the current-mode controller are reduced to
that of a single-pole system unlike the double pole in
voltage-mode control.
The devices use a current-mode control loop where the
output of the error amplifier (COMP) is compared to the
current-sense voltage at CS. When the current-sense
signal is lower than the noninverting input of the CPWM
comparator, the output of the CPWM comparator is low
and the switch is turned on at each clock pulse. When
the current-sense signal is higher than the inverting input
of the CPWM, the output of the CPWM comparator goes
high and the switch is turned off.
Undervoltage Lockout
The devices provide a UVLO/EN input. The threshold
for UVLO is 1.23V with 60mV hysteresis. Before any
operation can commence, the voltage on UVLO/EN has
to exceed 1.23V. The UVLO circuit keeps the CPWM
comparator, ILIM comparator, oscillator, and output dri-
ver shut down to reduce current consumption (see the
Functional Diagram
).
Use this UVLO/EN input to program the input-supply
start voltage. For example, a reasonable start voltage
for a 36V to 72V telecom range is usually 34V.
Calculate the resistor-divider values, R2 and R3 (see
Figure 1) by using the following formulas:
where I
UVLO
is the UVLO/EN input current (50nA max),
and V
ULR2
is the UVLO/EN wake-up threshold (1.23V).
V
IN
is the value of the input-supply voltage where the
power supply must start. The value of R3 is calculated
to minimize the voltage-drop error across R2 as a result
of the input bias current of the UVLO/EN input.
MAX17500 Bootstrap UVLO
In addition to the externally programmable UVLO func-
tion offered in both devices, the MAX17500 includes an
internal bootstrap UVLO that is very useful when
designing high-voltage power supplies (see the
Functional Diagram
). This allows the device to bootstrap
itself during initial power-up. The MAX17500 attempts to
start when V
IN
exceeds the bootstrap UVLO threshold
of 21.6V. During startup, the UVLO circuit keeps the
CPWM comparator, ILIM comparator, oscillator, and
output driver shut down to reduce current consumption.
Once V
IN
reaches 21.6V, the UVLO circuit turns on the
CPWM and ILIM comparators, the oscillator, and allows
the output driver to switch. If V
IN
drops below 1.17V, the
UVLO circuit shuts down the CPWM comparator, ILIM
comparator, oscillator, and output driver returning the
MAX17500 to the low-current startup mode.
Startup Operation
The MAX17499 starts up when the voltage at IN
exceeds 9.5V and the UVLO/EN input is greater than
1.23V. However, the MAX17500 requires that, in addi-
tion to meeting the specified startup conditions for the
MAX17499, the voltage at IN exceeds the bootstrap
UVLO threshold of 21.6V.
