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ACPL-K34T-000E

P1-P3P4-P6P7-P9P10-P12P13-P15
10
Application Information
Typical High Speed MOSFET Gate Drive Circuit
Figure 16. Typical high-speed MOSFET gate drive circuit
Anti-Cross Conduction Drive
One of the many benets of using ACPL-K34T is the ease to implement anti-cross conduction drive between the high
side and low side gate drivers to prevent shoot through event. This safety interlock drive can be realized by interlock-
ing the output of buer U5 and U6 to both high and low side gate drivers, as shown in Figure 16. However, due to the
propagation delay dierence between optocouplers, certain amount of dead time has to be added to ensure sucient
dead time at MOSFET gate. Refer to Dead Time and Propagation Delay section for more details.
Recommended LED Drive Circuits
Common mode noise exists whenever there is a dierence in the ground level of the optocoupler’s input control cir-
cuitry and output control circuitry. Figure 17 and 18 show recommended LED drive circuits for high common mode
rejection (CMR) performance of the optocoupler gate driver. Split limiting resistors are used to balance the impedance
at both anode and cathode of the input LED for high common mode noise rejection (see Figure 15).
Open drain and open collector drive circuits showed in Figure 19 are not recommended. During the o state of the MOS-
FET/transistor, cathode of the input LED sees high impedance and becomes sensitive to noise. In any cases, if designer
still prefers to use single MOSFET/transistor drive over the recommended CMOS buer drive showed in Figure 17 and
18, designer can choose alternative circuits showed in Figure 20; however M1/Q1 in Figure 20 drive circuits will shunt
current during LED o state, which result in more power consumption.
Drive Power
If CMOS buer is used to drive LED, it is recommended to connect the CMOS buer at the LED cathode. This is because
the sinking capability of the NMOS is usually more than the driving capability of the PMOS in a CMOS buer.
Drive Logic
Designer can congure LED drive circuits for non-inverting and inverting logic as recommended in Figure 17 and 18.
External power supply, V
DD1
has to be connected to the CMOS buer for the inverting and non-inverting logic to work.
If V
DD1
supply is lost, LED will be permanently o and output will be at low.
+5V
Rin1
Rin3
uP
VDD
PHA
10V
10u
D1
10uF
Q1
4.7Ω
4.7Ω
+12V
10u
Q2
10u
Q3
4.7Ω
4.7Ω
10u
Q4
D2
Rin4
Rin2
0.1uF
ACPL-K34T
+HVDC
- HVDC
U1
U2
U3
U4
PHA
U5
U6
PHA
PHA
LED(U1)
LED(U2)
Anti-cross conduction drive logic
ACPL-K34T
ACPL-K34T
ACPL-K34T
AN
NC
CA
NC
VCC
V
OUT
V
EE
NC
AN
NC
CA
NC
VCC
V
OUT
V
EE
NC
AN
NC
CA
NC
VCC
V
OUT
V
EE
NC
AN
NC
CA
NC
VCC
V
OUT
V
EE
NC
11
Figure 19(a) and Figure 19(b). Not recommended – Open drain/open collector drive circuit
Figure 20(a) and Figure 20(b). Alternative LED drive circuits to replace Figure 19(a) and 19(b)
Bypass and Reservoir Capacitors
Supply bypass capacitors are necessary at the input buer and ACPL-K34T output supply pin. A ceramic capacitor with
the value of 0.1 µF is recommended at the input buer to provide high frequency bypass, which also helps to improve
CMR performance. At the output supply pin (V
CC
– V
EE
), it is recommended to use a 10 µF, low ESR and low ESL capacitor
as a charge reservoir to supply instant driving current to MOSFET at V
OUT
during switching.
Figure 17. Recommended non-inverting drive circuit
Figure 18. Recommended inverting drive circuit
Figure 19(b)
Figure 19(a)
Figure 20(a)
Figure 20(b)
V
DD1
Ro
V
DD1
10 µF
ISOLATION
0.1 µF
V
CC
V
OUT
V
EE
AN
CA
V
DD1
Ro
V
DD1
10 µF
ISOLATION
0.1 µF
V
CC
V
OUT
V
EE
AN
CA
V
DD1
10 µF
R
in
ISOLATION
0.1 µF
V
CC
V
OUT
V
EE
AN
CA
V
DD1
10 µF
R
in
ISOLATION
ACPL-K34T
0.1 µF
AN
CA
V
CC
V
OUT
V
EE
V
DD1
10 µF
R
in2
ISOLATION
0.1 µF
R
in1
V
CC
V
OUT
V
EE
AN
CA
M1
V
DD1
10 µF
R
in2
ISOLATION
0.1 µF
R
in1
V
CC
V
OUT
V
EE
AN
CA
Q1
ACPL-K34T
ACPL-K34TACPL-K34T
ACPL-K34T
ACPL-K34T
V
DD1
= 5 V ± 10%
Ratio R
in1
: (R
in2
+R
o
) = 1.5:1
Recommended R
o
+R
in1
+R
in2
= 350 Ω
Ratio R
in1
: (R
in2
+R
o
) = 1.5:1
V
DD1
= 5 V ± 10%
V
DD1
= 5 V ± 10% V
DD1
= 5 V ± 10%
R
in2
R
in1
R
in2
R
in1
Recommended R
o
+R
in1
+R
in2
= 350 Ω
Ratio R
in1
: R
in2
= 1.5:1
Recommended R
in1
+R
in2
= 350 Ω
Ratio R
in1
: R
in2
= 1.5:1
Recommended R
in1
+R
in2
= 350 Ω
12
Initial Power Up and UVLO Operation
Insucient gate voltage to MOSFET can increase turn on resistance of MOSFET, resulting in large power loss and MOS-
FET damage due to high heat dissipation. ACPL-K34T monitors the output power supply constantly. During initial power
up, the ACPL-K34T requires maximum 50 µs of initial startup time for the internal bias and circuitry to get ready. The gate
driver output (V
OUT
) is hold at o state during initial startup time. Thereafter, when the output power supply is lower
than under voltage lockout (V
UVLO-
) threshold, gate driver output will shut o to protect MOSFET from low voltage bias.
When the output power supply is more than the V
UVLO+
threshold, V
OUT
is released from low state and it follows the
input LED drive signal, as shown in Figure 21.
Figure 21. ACPL-K34T initial power-up and UVLO operation
Figure 22a. Negative DTD reduces original DT
Dead Time Distortion and Propagation Delay
Dead time is the period of time during which both high side and low side power transistors (shown as Q1 and Q2 in Fig-
ure 16) are o. Any overlap in Q1 and Q2 conduction will result in a shoot-through event and large short circuit current
will ow through the power devices between the high side and low side power rail.
ACPL-K34T includes a Dead Time Distortion (DTD) specication intended to help designers optimize dead time in a
power inverter design. A negative DTD value will decrease the system dead time, and so a negative DTD must be com-
pensated by adding extra dead time to the design. Figure 22a shows that dead time after optocoupler is reduced by
negative DTD. On the other hand, a positive DTD will add to the system original dead time, and so a positive DTD will
cause dead time redundancy to the system. Figure 22b shows that dead time after optocoupler is increased by positive
DTD.
VCC
Vin(LED)
V
OUT
Initial startup
time
V
UVLO -
V
UVLO+
V
UVLO +
Figure 22b. Positive DTD increased original DT
Figure 22. Dead Time and Propagation Delay Waveforms
P1-P3P4-P6P7-P9P10-P12P13-P15

ACPL-K34T-000E

Mfr. #:
Buy ACPL-K34T-000E
Manufacturer:
Broadcom / Avago
Description:
High Speed Optocouplers OPTOCOUPLER AUTOMOTIVE LF
Lifecycle:
New from this manufacturer.
Delivery:
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