NCP81382
www.onsemi.com
13
For Use with Controllers with 2−Level PWM and Zero Current Detection Capability:
Table 5. LOGIC TABLE − 2−STATE PWM CONTROLLERS WITH ZCD
PWM SMOD# ZCD_EN GH GL
H L X ON OFF
L L H OFF ON
L L L OFF OFF
This section describes operation with controllers that do
not have 3−level PWM output capability but are capable of
zero current detection during discontinuous conduction
mode (DCM).
The SMOD# pin needs to be pulled low (below
V
SMOD#_LO
).
When PWM is high, GH will always be in the high state
and GL will always be in the low state, regardless of the state
ZCD_EN is in.
When PWM is in the low state, the state of ZCD_EN
determines whether the converter is placed into diode
emulation mode. When the controller detects positive
inductor current, ZCD_EN should be in the high state,
allowing the LS FET to be on and conducting. Once the
controller detects zero or negative current, ZCD_EN should
be placed into the low state, turning off the LS FET. With the
LS FET turned off, the body diode of the LS FET allows any
positive current that may still be flowing to reach zero, but
prevents the current from flowing in the negative direction.
Figure 11. Timing Diagram − 2−state PWM Controller, with ZCD
GL
GH
PWM
ZCD_EN
IL 0 A
SMOD# 0 V
SMOD# = Low
Low ZCD_EN
pulls GL low.
Controller detects zero
current → Sets ZCD_EN low.
