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HTF16C64_128_256x64AG.fm - Rev. D 5/06 EN
10 ©2003 Micron Technology, Inc. All rights reserved.
512MB, 1GB, 2GB: (x64, DR) 240-Pin DDR2 SDRAM UDIMM
Electrical Specifications
Notes: 1. a = Value calculated as one module rank in this operating condition, and all other module
ranks in I
DD2P (CKE LOW).
2. b = Value calculated reflects all module ranks in this operating condition.
Tabl e 8: DDR2 IDD Specifications and Conditions – 1GB
Values shown for DDR2 SDRAM components only
Parameter/Condition Symbol -80E -667 -53E -40E Units
Operating one device bank active-precharge current;
t
CK =
t
CK (IDD),
t
RC =
t
RC (IDD),
t
RAS =
t
RAS MIN (IDD); CKE is HIGH, S# is HIGH between
valid commands; Address bus inputs are switching; Data bus inputs are
switching
IDD0
a
856 776 696 696 mA
Operating one device bank active-read-precharge current; I
OUT =
0mA; BL = 4, CL = CL (IDD), AL = 0;
t
CK =
t
CK (IDD),
t
RC =
t
RC (IDD),
t
RAS =
t
RAS MIN (IDD),
t
RCD =
t
RCD (IDD); CKE is HIGH, S# is HIGH between valid
commands; Address bus inputs are switching; Data pattern is same as
I
DD4W
I
DD1
a
976 896 816 776 mA
Precharge power-down current; All device banks idle;
t
CK =
t
CK (IDD);
CKE is LOW; Other control and address bus inputs are stable; Data bus
inputs are floating
I
DD2P
b
112 112 112 112 mA
Precharge quiet standby current; All device banks idle;
t
CK =
t
CK (IDD);
CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable;
Data bus inputs are floating
I
DD2Q
b
800 720 640 560 mA
Precharge standby current; All device banks idle;
t
CK =
t
CK (IDD); CKE is
HIGH, S# is HIGH; Other control and address bus inputs are switching;
Data bus inputs are switching
I
DD2N
b
880 800 720 640 mA
Active power-down current; All device banks open;
t
CK
=
t
CK (IDD); CKE is LOW; Other control and address bus
inputs are stable; Data bus inputs are floating
Fast PDN exit
MR[12] = 0
I
DD3P
b
640 560 480 400 mA
Slow PDN exit
MR[12] = 1
192 192 192 192 mA
Active standby current; All device banks open;
t
CK =
t
CK (IDD),
t
RAS =
t
RAS MAX (IDD),
t
RP =
t
RP (IDD); CKE is HIGH, S# is HIGH between valid
commands; Other control and address bus inputs are switching; Data bus
inputs are switching
IDD3N
b
1,120 1,040 880 720 mA
Operating burst write current; All device banks open; Continuous
burst writes; BL = 4, CL = CL (I
DD), AL = 0;
t
CK =
t
CK (IDD),
t
RAS =
t
RAS MAX
(IDD),
t
RP =
t
RP (IDD); CKE is HIGH, S# is HIGH between valid commands;
Address bus inputs are switching; Data bus inputs are switching
IDD4W
a
1,616 1,416 1,1176 976 mA
Operating burst read current; All device banks open; Continuous burst
reads, I
OUT = 0mA; BL = 4, CL = CL (IDD), AL = 0;
t
CK =
t
CK (IDD),
t
RAS =
t
RAS
MAX (IDD),
t
RP =
t
RP (IDD); CKE is HIGH, S# is HIGH between valid
commands; Address bus inputs are switching; Data bus inputs are
switching
I
DD4R
a
1,696 1,496 1,216 976 mA
Burst refresh current;
t
CK =
t
CK (IDD); REFRESH command at every
t
RFC
(I
DD) interval; CKE is HIGH, S# is HIGH between valid commands; Other
control and address bus inputs are switching; Data bus inputs are
switching
IDD5
b
3,680 2,880 2,720 2,640 mA
Self refresh current; CK and CK# at 0V; CKE ≤ 0.2V; Other control and
address bus inputs are floating; Data bus inputs are floating
I
DD6
b
112 112 112 112 mA
Operating device bank interleave read current; All device banks
interleaving reads, I
OUT = 0mA; BL = 4, CL = CL (IDD), AL =
t
RCD (IDD) - 1 ×
t
CK (IDD);
t
CK =
t
CK (IDD),
t
RC =
t
RC (IDD),
t
RRD =
t
RRD (IDD),
t
RCD =
t
RCD
(I
DD); CKE is HIGH, S# is HIGH between valid commands; Address bus
inputs are stable during DESELECTs; Data bus inputs are switching; See
I
DD7 conditions in component data sheet for detail
I
DD7
a
2,456 1,976 1,856 1,816 mA
