PDF: 09005aef80f09084/Source: 09005aef80f09068 Micron Technology, Inc., reserves the right to change products or specifications without notice.
HTF16C64_128_256x64AG.fm - Rev. D 5/06 EN
9 ©2003 Micron Technology, Inc. All rights reserved.
512MB, 1GB, 2GB: (x64, DR) 240-Pin DDR2 SDRAM UDIMM
Electrical Specifications
Notes: 1. a = Value calculated as one module rank in this operating condition, and all other module
ranks in IDD2P (CKE LOW).
2. b = Value calculated reflects all module ranks in this operating condition.
Tabl e 7: DDR2 IDD Specifications and Conditions – 512MB
Values shown for DDR2 SDRAM components only
Parameter/Condition Symbol -667 -53E -40E Units
Operating one device bank active-precharge current;
t
CK =
t
CK (IDD),
t
RC =
t
RC (IDD),
t
RAS =
t
RAS MIN (IDD); CKE is HIGH, S# is HIGH between valid
commands; Address bus inputs are switching; Data bus inputs are switching
I
DD0
a
680 680 640 mA
Operating one device bank active-read-precharge current; IOUT = 0mA; BL
= 4, CL = CL (I
DD), AL = 0;
t
CK =
t
CK (IDD),
t
RC =
t
RC (IDD),
t
RAS =
t
RAS MIN (IDD),
t
RCD =
t
RCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus
inputs are switching; Data pattern is same as IDD4W
I
DD1
a
760 760 720 mA
Precharge power-down current; All device banks idle;
t
CK =
t
CK (IDD); CKE is
LOW; Other control and address bus inputs are stable; Data bus inputs are
floating
I
DD2P
b
80 80 80 mA
Precharge quiet standby current; All device banks idle;
t
CK =
t
CK (IDD); CKE is
HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus
inputs are floating
I
DD2Q
b
560 560 400 mA
Precharge standby current; All device banks idle;
t
CK =
t
CK (IDD); CKE is HIGH,
S# is HIGH; Other control and address bus inputs are switching; Data bus inputs
are switching
I
DD2N
b
640 560 480 mA
Active power-down current; All device banks open;
t
CK =
t
CK
(I
DD); CKE is LOW; Other control and address bus inputs are
stable; Data bus inputs are floating
Fast PDN exit
MR[12] = 0
IDD3P
b
480 400 320 mA
Slow PDN exit
MR[12] = 1
96 96 96 mA
Active standby current; All device banks open;
t
CK =
t
CK (IDD),
t
RAS =
t
RAS
MAX (IDD),
t
RP =
t
RP (IDD); CKE is HIGH, S# is HIGH between valid commands;
Other control and address bus inputs are switching; Data bus inputs are
switching
IDD3N
b
800 640 480 mA
Operating burst write current; All device banks open; Continuous burst
writes; BL = 4, CL = CL (I
DD), AL = 0;
t
CK =
t
CK (IDD),
t
RAS =
t
RAS MAX (IDD),
t
RP =
t
RP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs
are switching; Data bus inputs are switching
I
DD4W
a
1,560 1,320 1,040 mA
Operating burst read current; All device banks open; Continuous burst reads,
I
OUT = 0mA; BL = 4, CL = CL (IDD), AL = 0;
t
CK =
t
CK (IDD),
t
RAS =
t
RAS MAX (IDD),
t
RP =
t
RP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus
inputs are switching; Data bus inputs are switching
I
DD4R
a
1,480 1,240 960 mA
Burst refresh current;
t
CK =
t
CK (IDD); REFRESH command at every
t
RFC (IDD)
interval; CKE is HIGH, S# is HIGH between valid commands; Other control and
address bus inputs are switching; Data bus inputs are switching
I
DD5
b
2,880 2,720 2,640 mA
Self refresh current; CK and CK# at 0V; CKE ≤ 0.2V; Other control and address
bus inputs are floating; Data bus inputs are floating
IDD6
b
80 80 80 mA
Operating device bank interleave read current; All device banks
interleaving reads, I
OUT = 0mA; BL = 4, CL = CL (IDD), AL =
t
RCD (IDD) - 1 ×
t
CK
(I
DD);
t
CK =
t
CK (IDD),
t
RC =
t
RC (IDD),
t
RRD =
t
RRD (IDD),
t
RCD =
t
RCD (IDD); CKE is
HIGH, S# is HIGH between valid commands; Address bus inputs are stable during
DESELECTs; Data bus inputs are switching; See I
DD7 conditions in component
data sheet for detail
I
DD7
a
2,040 1,960 1,880 mA