CAT1163
© 2009 SCILLC. All rights reserved. 1 Doc. No. MD-3003 Rev. I
Characteristics subject to change without notice
Supervisory Circuits with I
2
C Serial CMOS EEPROM,
Precision Reset Controller and Watchdog Timer (16K)
FEATURES
Watchdog timer input (WDI)
400kHz I
2
C bus compatible
2.7V to 6.0V operation
Low power CMOS technology
16-Byte page write buffer
Built-in inadvertent write protection
— V
CC
lock out
— Write protect pin, WP
Active high or low reset
— Precision power supply voltage monitor
— 5V, 3.3V and 3V systems
— Five threshold voltage options
1,000,000 Program/Erase cycles
Manual reset
100 Year data retention
8-pin DIP or 8-pin SOIC
Commercial and industrial temperature ranges
For Ordering Information details, see page 13.
DESCRIPTION
The CAT1163 is a complete memory and supervisory
solution for microcontroller-based systems. A serial
EEPROM memory (16K) with hardware memory write
protection, a system power supervisor with brown out
protection and a watchdog timer are integrated
together in low power CMOS technology. Memory
interface is via an I
2
C bus.
The 1.6-second watchdog circuit returns a system to a
known good state if a software or hardware glitch
halts or “hangs” the system. The CAT1163 watchdog
monitors the WDI input pin.
The power supply monitor and reset circuit protects
memory and system controllers during power up/down
and against brownout conditions. Five reset threshold
voltages support 5V, 3.3V and 3V systems. If power
supply voltages are out of tolerance reset signals
become active, preventing the system microcontroller,
ASIC or peripherals from operating. Reset signals
become inactive typically 200ms after the supply
voltage exceeds the reset threshold level. With both
active high and low reset signals, interface to
microcontrollers and other ICs is simple. In addition, a
reset pin can be used as debounced input for push-
button manual reset capability.
The CAT1163 memory features a 16-byte page. In
addition, hardware data protection is provided by a
write protect pin WP and by a V
CC
sense circuit that
prevents writes to memory whenever V
CC
falls below
the reset threshold or until V
CC
reaches the reset
threshold during power up.
Available packages include an 8-pin DIP and a
surface mount, 8-pin SO package.
PIN CONFIGURATION
PDIP 8 Lead
SOIC 8 Lead
WDI 1 8 V
CC
RESET
¯¯¯¯¯¯
2 7 RESET
WP 3 6 SCL
GND 4 5 SDA
CAT1163
PIN FUNCTIONS
Pin Name Function
WDI Warchdog Timer Input
RESET
¯¯¯¯¯¯
Active Low Reset I/O
WP Write Protect
GND Ground
SDA Serial Data/Address
SCL Clock Input
RESET
Active High Reset I/O
V
CC
Power Supply
